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In the context of Shared Memory Multiprocessor (SMP) systems with different cache levels, if a cache miss occurs in the first private cache but is followed by a hit in the second shared cache, would this situation lead to a penalty or delay in data retrieval?

So far all question's I've solved involve a data or instruction cache and some information about the byte, then assembly code. Everything I have to do is analyse miss rate or hit rat or CPI etc. So my question is what about the case I am mentioning here. How would someone go about solving it, what type of information is needed in order to solve it? (I'm prepareing for an Exam).

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If another thread has modified the logical memory belonging to that cache line then there will be a delay.

It is unlikely that the processor can move data directly from one private cache to another. So if the data is changed in processor B’s private cache, that processor needs to be notified, then it writes the cache line to the shared cache, then processor A reads it from there. So a delay.

To detect the situation, one method is to empty the shared cache when a line is modified in the private cache. That’s no problem since the data must not be used anyway. So A will try to read from the next cache level, and things are handled there where it is less time critical.

There are also usually instructions that force writing data to memory, and you would use them for data that is supposed to be changed.

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  • $\begingroup$ Thanks for the answer, but if there is a hit in the second cache tho? I know that L2 cache is still faster than RAM but do I count that occasion like an oridinary hit or miss? BTW those cases when the cores are not invalidating each other's cache lines. $\endgroup$
    – First_1st
    Commented Jan 13 at 9:27

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