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I recently had an interview to identify all of the hazards in the following instruction set. I was told by the interviewer that there was some hazard between instructions i3 and i4 and it's not a RAW hazard on R4 so I'm a little lost. Any insight? Thanks!

1: ADD R1, R2, R3
2: ADD R4, R5, R1
3: LOAD R4, R3(src addr)
4: STORE R7(dst addr), R4
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    $\begingroup$ Instruction set would be the set of all machine instructions, hazards are discussed in the context of machine programs, instruction sequences where sequential. Please add to your question which operand is the destination operand. Or name the architecture if it can be considered well-known. $\endgroup$
    – greybeard
    Commented Jan 18 at 6:09
  • $\begingroup$ @greybeard I wasn't really given a specific architecture to go off of, just told these are general instructions. The first operand can be considered the destination operand though (i.e. for the first instruction the result of R2 + R3 goes into R1 or R3(src addr) gets loaded into R4). $\endgroup$
    – johnbon
    Commented Jan 18 at 17:16
  • $\begingroup$ Not that I see any connection to hazards, but without an architecture/a detailed definition of the effects of ADD R4, R5, R1, I see no way of knowing whether in i2 just the store is a "dead" one, or the whole instruction's sole effect is on timing, if that. $\endgroup$
    – greybeard
    Commented Jan 18 at 18:57
  • $\begingroup$ I guess just assume its RISC architecture. Some of the other hazards that I found where RAW between I1 and I2 on R1. I was also told the hazard occurred specifically between I3 and I4 with something to do with load followed by store. $\endgroup$
    – johnbon
    Commented Jan 18 at 19:04

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