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At first I thought it is obvious, since the NOP instruction does not have any operand, we say it is zero-operand instruction. But then looking on the zero-operand instruction,

But looking after the definition I am confused to classify the instruction into $n$-operand category, where $n \in \{0, 1, 2, 3\}$ ref

These instructions do not specify any operands or addresses. Instead, they operate on data stored in registers or memory locations implicitly defined by the instruction.

What I know so far: Based on the number of operands in the instructions (including literals) we classify the $n$-operand class.

Update 0x00:
Is the NOP instruction zero-operand? If no then why (it is not using any operand), if yes, then why (it is not using any data stored in stack / register memory location). I am stuck in this dilemma. If the bracket part doesn't make sense to you, you may choose to ignore it

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  • $\begingroup$ I don't see any definition of $n$-operand in the reference you provided. $\endgroup$
    – Steven
    Jan 20 at 13:26
  • $\begingroup$ From $n$ I mean 0,1,2,3 operands. Consider it as number of operands $\endgroup$
    – tbhaxor
    Jan 20 at 13:28
  • $\begingroup$ Can you explain what the confusion is? Clearly the NOP instruction does not specify any operand. Also the quoted block specifically refers to instructions with $0$-operands. $\endgroup$
    – Steven
    Jan 20 at 13:30
  • $\begingroup$ Is the NOP instruction zero-operand? If no then why (it is not using any operand), if yes, then why (it is not using any data stored in stack / register memory location). I am stuck in this dilemma. If the bracket part doesn't make sense to you, you may choose to ignore it. $\endgroup$
    – tbhaxor
    Jan 20 at 13:39

3 Answers 3

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A 0-operand instruction is simply an instruction that takes no operand. As a result, if such an instruction changes some data either in memory or in some register, the corresponding address or register name is implicitly determined by the instruction itself at time of execution (e.g., the affected memory location might depend on the contents of some register).

I think that your confusion stems from the fact that the "definition" for 0-operand instruction is sloppily written.

A 0-operand instruction is not required to operate on any data nor register. What the definition is trying to say is that if such an instruction operates on data/registers then the address of the data/the involved register must be implicitly determined (duh).

NOP is a $0$-operand instruction as it does not take any operand.

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  • $\begingroup$ So based my understanding, PUSH 10 is 2 operand, as it takes 10 as explicit and updates to ESP implicitly. The decomposition would be SUB ESP, 0x4 followed by MOV [ESP],10. And similarly INC EAX is one operand instruction. Please correct me if I am wrong $\endgroup$
    – tbhaxor
    Jan 21 at 11:40
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To name one example, one of the NOPs in x86 (there's a bunch!) is encoded as 90. It's a special case of the family of instructions encoded as 90+rd meaning that it encodes one operand in the 3 bottom bits of the opcode, in 90 those three bits are obviously zero, which encodes eax. The 90+rd family encodes xchg eax, r so 90 encodes xchg eax, eax, swapping a register with itself. So it doesn't do anything, but how many operands is that? At the assembly level, 2 if you write xchg eax, eax and 0 if you write nop. At the machine code level, 1. 0 operands if you consider how many operands are "logically" used.

To name a couple of other examples, the "normal" NOP in MIPS can also be decoded as sll $r0, $r0, 0, RISC-V appoints addi x0, x0, 0 for that role, and x86 has a "long NOP" 0F 1F /0 where /0 indicates that a ModRM byte follows and its r field has to be set to zero as part of the opcode. This NOP can encode a memory operand, so nop dword ptr es:[eax + 2 * edx + 4] is a valid instruction that can be encoded as 26 0f 1f 44 50 04. How many operands does it have? Maybe 1 since it has only the one memory operand? Maybe 4, counting the segment override and the 3 "parts" of the address separately? Maybe 3, not counting the segment override (are overrides operands? maybe not) but still counting the others? Maybe 0 because none of those things are actually used in the execution of the instruction? I wouldn't want to give any definitive answer, even if I did it would just be my opinion.

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A NOP instruction is used to fill program space while having no side effect. This is done for example to make a loop start at the beginning of a cache line to run faster. The AMD processor manuals describe 1 byte to 9 byte NOP instruction. None is officially called NOP.

For example “add constant 0 to register x” would be a NOP instruction. It also has a constant input, a register input, and a register output. Or “set register x to the OR of register x with the contents of register x”, this time two inputs.

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  • $\begingroup$ This is so not what I asked. But thanks for your efforts. $\endgroup$
    – tbhaxor
    Jan 21 at 11:35
  • $\begingroup$ The answer is not always what you ask for. PowerPC and POWER for example have no NOP instruction in the processor. $\endgroup$
    – gnasher729
    Jan 21 at 19:07

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