I'm currently implementing a RISC prozessor in a HDL and realized that I seem to have a somewhat incorrect understanding of how pipeling works for control signals. Here's my general understanding:

  • Ideally, each phase should take exactly one clock cycle (this is the case in my implementation)
  • The pipeline registers hold the data and control signals for exactly one clock cycle. They are only controlled by the clock itself and forward the data to the next phase each clock signal. There is no "control input" to the pipeline registers which determines when a register saves or forwards data, this is only based on clock edge (is this correct?)

My question therefore is: If each execution takes one cycle and data/control signals move through the pipeline registers per cycle, what "happens" to the control signals during clock phases where data is being processed, eg. EX?

Take the following picture, with data displayed as red, and control signals depicted as green. If I were to build my cpu like this, the control signals would move to the second register before the ALU has even finished execution, right? Would I not need extra registers in which control signals are stored while the data is being processed, so that the data and control are always in sync?

I'm sorry if this is somewhat of a noob question but I'm generally struggling with understanding this. If anyone could point out what I'm missing, I'd be very thankful.

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