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i'm designing a CPU from scratch so i want it to be small. i decided to go with 4 bits registers. but 16 words of memory is a bit too small and i want more so i guess i need wider address bus (ie. 6). that raises a few questions:

  1. how should i set address to memory address register?

    • using multiple data registers at the same time?
    • by having a dedicated 'construction-site address register), setting that address using multiple instructions and only then do jump?
  2. how to read an address from an instruction? in my program i want to have instruction jump 0x2E. but i read my program word by word. i can't fit opcode and 6-bit operand in a 4 bit instruction. i can't do it even if my address bus is the same as data bus. how this problem is solved in practice?

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Look at early Intel processors designed under similar conditions, as 4004, 8008, 8051, 8080. In 8080, for example, 16-bit address is combined of register pairs like HL (so H+L), BC (B+C), DE (D+E), which also could be accessed separately (and there were a few 16-bit operations, mainly for address handling).

In 8086, a real address is combined of a 16-bit segment shifted left by 4 bits plus a 16-bit offset. The result is 20 bits wide.

In some successors of Mostek 6502, two special registers can specify high byte of address of "zero page" (memory operand for insrtructions with 1-byte address) and of stack.

To sum up, different designs from 1970s are all you need:)

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  • $\begingroup$ That still happened in the 2000’s. There were 32 bit Intel processors with up to 64 GB of RAM usable instead of just 4GB. The trick: There was 4GB of RAM per process and the OS had a 36 bit address for each process’s memory. So you could in theory have 16 processes each using 4GB. $\endgroup$
    – gnasher729
    Apr 8 at 12:38
  • $\begingroup$ @gnasher729 Yep. A case of physical address wider than virtual one is not only x86-with-PSE but also PDP-11, BESM-6, and, surprise, the most modern one - RISC-V! The latter translates 32-bit virtual address to 34-bit physical one (Sv32 scheme). I don't know a rationale. $\endgroup$
    – Netch
    Apr 9 at 13:15
  • $\begingroup$ Imagine you have 4GB for RAM used as memory, 4GB RAM used as a RAM disk, some gigabyte for controlling hardware. Or you have four slots for RAM, each with 4GB physical address space, but holding smaller RAM chips. Four 1GB chips could be a lot cheaper than one 4GB chip. So your memory would cover the first, fifth, ninth and thirteenth gigabyte. $\endgroup$
    – gnasher729
    Apr 10 at 21:51
  • $\begingroup$ @gnasher729 Complexity of handling with such a bank switching when you can't put all stuff into one plain space - led to mass switching to 64-bit addressing starting with 1.5GB RAM. $\endgroup$
    – Netch
    Apr 12 at 6:15

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