# MIPS: How can the least 2 significant bits of a 32-bit address specify a byte?

I was reading Computer Architecture Organization and Design by David A. Patterson and John L. Hennessy. Specifically, I was reading chapter 5, section 5.3, Basics of Caches. I read the following excerpt:

The index of a cache block, together with the tag contents of that block, uniquely specifies the memory address of the word contained in the cache block. Because the index field is used as an address to reference the cache, and because an $$n$$-bit field has $$2^n$$ values, the total number of entries in a direct-mapped cache must be a power of 2. In the MIPS architecture, since words are aligned to multiples of four bytes, the least significant two bits of every address specify a byte within a word. Hence, the least significant two bits are ignored when selecting a word in the block.

It was the bolded section that confused me. How can 2 bits in a 32-bit/4 byte address(that is one word in MIPS) specify a byte, that being 8 bits?

Using two bits you can count from 0 to 3 (four numbers), so if you want to specify a byte in a four byte word two bits are enough.

If you read "the least significant two bits are ignored" as "the least significant two bits are set to zero" it might be easier to understand. Then the resulting address is simply $$x_{31}x_{30}...x_200$$, i.e. $$x_{31}x_{30}...x_2$$ multiplied by $$2^2 = 4$$, ensuring that you only address whole words (4 byte blocks). Not zeroing the last two bits would allow you to express all possible addresses in your address space again, not just addresses that are multiples of 4.

• I do understand your second paragraph. However it is the first one that I’m confused in. I still don’t understand how the least significant 2 bits can specify a byte in a 4 byte word :( Commented Apr 6 at 11:19
• now in the book it is also mentioned as "Word Alignment", each address is multiple of 4(in binary 2 least significant bits are 00) now this address gives you byte not the word, because of byte addressability, however you want to fetch entire word to do something(store word, load word, fetch instruction), so let's solve this like this: have byte addressed memory with only multiple of 4 addresses, this will give you address of specific byte, however by changing 2 least significant bits 00 -> 01 -> 10 -> 11 you will get 4 different address and 4 different bytes(and 4 bytes will create word). Commented Apr 6 at 12:28
• $x_{31}x_{30}...x_200$ now this gives you specific byte, now consider $x_{31}x_{30}...x_201$ and $x_{31}x_{30}...x_210$ and $x_{31}x_{30}...x_211$ if you concatenate all bytes of those 4 addresses, you will get entire 32-bit word. Commented Apr 6 at 12:29
• @JuanDeCastr All addresses can be written as $4m + n$ for $0 \leq n < 3$. Since all words are 4 bytes long, having an address like $4m + n$ means you are somewhere in the $m$th word. If $n = 0$ you're at the first byte of the $m$th word, $n = 1$ is the second, up to $n = 3$ which is the fourth. And as it turns out, when you write these addresses in binary the first two bits will always exactly equal $n$ (they are the mod 4 of the address, see math boys comment) and the $m$ will always equal the remaining digits. Commented Apr 6 at 12:49
• So if I understand correctly: MIPS uses byte-addressable memory, meaning that to have a word, you must address 4 bytes, the first address having 00 as the 2 last significant bits(multiple of 4 in binary). Because a word is 4 bytes and each address holds 1 byte of information, you must have 4 addresses to specify a word, each specifying a byte. And it is those 2 last significant bits(based on 00, 01, 10 and 11) that specify any of those bytes out of the 4 bytes. Commented Apr 6 at 13:12