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With byte addressing, the CPU can access a single byte. But how does this access happen during alignment? As I understand it, if a CPU needs to read an unaligned byte, it reads the word starting from the aligned byte, then discards the excess and stores the data in the lowest byte of some register. If I'm wrong, then explain how it actually works.

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  • $\begingroup$ Yes, this is correct. The details depend on a specific CPU. $\endgroup$ Commented Apr 16 at 8:20

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Let’s say you have an old CPU with 4 byte registers and 4 byte memory bus. Reading from memory must be aligned, so you can read bytes 100-103, 104-107 etc for example. If your processor wants bytes 103-106, then it has to read bytes 100-103, remember the last byte, read bytes 104-107, take the first three bytes, and combine those four bytes.

A more modern processor reads data into cache lines of for example 64 bytes. So one cache line holds bytes 0 to 63, one holds 64 to 127 etc. Any 4 bytes starting at an address from 64 to 124 can be read from the cache line with bytes 64 to 127. For data starting at 125 to 127, the processor needs two cache lines in memory and accesses them both.

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  • $\begingroup$ I'm not asking about reading an unaligned word, I'm asking about how the CPU uses byte addressing (that is, how the CPU reads a single byte), having, say, 32-bit registers and a 32-bit data bus, while referring only to aligned addresses. $\endgroup$
    – Slaycapь
    Commented Apr 16 at 7:52
  • $\begingroup$ A Single byte is always contained completely in one 32 bit aligned word. So there is no problem. $\endgroup$
    – gnasher729
    Commented Apr 16 at 8:38

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