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In the RISC-V specification, there is support for the conversion between floating point and integer numbers, in particular the fcvt* class of instructions. I'm wondering what the hardware implementation of these conversion processes require and how expensive they are.

If the community would be able to point me to some academic (or other) resources on how this conversion works at a hardware level, I would be very appreciative :)

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Look at denormalised double precision floating-point numbers. The lowest mantissa bit has a value of 2^-k for some fixed k.

Now take any floating-point number and multiply it by 2^-k. The result is a denormalised floating point number with all the mantissa bits in the right position. Now you just need to get a 64 bit mantissa instead of 53 bit, use twos complement instead of signed magnitude for negative numbers, get the rounding right, and handle numbers outside the valid range.

Maybe simpler: Adding 1.5 x 2^52 to x will store the integer part of x into the lowest 52 bits of the mantissa if -0.5 x 2^52 <= x <= 0.5 x 2^52 - 1. Just figure out what this operation will do and how to extend it to 64 bits. (Often useful if you want to round numbers in that range to an integer value. Very effective if you want to round a product).

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