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Suppose that a processor can address directly up to 4 Gigabyte main memory and can operate words with size 32 bit. Find how big should be the size of the "MAR" (memory address registers), "MDR" (memory data registers) and accumulator registers in this computer?

My answer: MDR is 32 bit wide since it exchanges data not only via the data bus but with the CPU data registers. How about MAR and accumulator? how are they related to the 4 gigabyte main memory?

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    $\begingroup$ I am NOT voting to close because the OP is asking a specific question. How are they related to the 4 gigabyte main memory? The OP is not asking for an answer to the problem but help to understand how to answer the problem. $\endgroup$ – Guy Coder Dec 7 '13 at 19:36
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This question is not so simple to answer. At first sight, 32 bit address registers seem to perfectly match 2^32 byte = 4 GB of physical memory. However, with 32 Bit you can also address more than 4 GB, like Physical Address Extension (PAE) does. The opposite way round means that you can access 4 GB with less than 32 bit address register.

The data registers are not related to the memory size at all in my opinion. The data registers are mainly an indicator how much data can be transferred at one time. If you want e.g. to crack SHA-512, then you could design a CPU which benefits from transferring 512 bit of data at one time, so you have 512 data registers.

The same SHA-512 cracker CPU brings us to the accumulator: ideally the CPU would also process 512 bit numbers in one cycle, so the accumulator is also 512 bit.

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  • $\begingroup$ Not directly, but it is awkward to have to handle pointers (addresses) in several pieces, so typically the registers would also be 32 bits. But take a look at the (horrible) segmentation nonsense in the intel 8086 (16 bits, but had 1MiB address space via 16 bit segment (shifted 4 bits) + 16 bit offset). $\endgroup$ – vonbrand Feb 25 '14 at 16:49

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