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I'm a newbie in computer science and would to understand how hardware interrupts work at the physical layer. I ask my question considering a specific example. When packet arrives at the network adapter, a hardware interrupt is raised. Wikipedia says that

an interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention.

I know that the OS will invoke a corresponding interrupt handler when the interrupt's type is detected. But I don't understand how the CPU detects and distinguishes incoming interrupts.

First, why CPU does know that the interrupt is coming from the network adapter and not from some other device?

Second, where are interrupt handlers registered in the CPU? Are there specific areas of the CPU that contain addresses for handlers registered by the OS?

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The CPU has specific pins on the outside to detect hardware interrupts.

Take for instance the 6502 used in the Apple II and c64 it has two interrupt pins:
IRQ on pin 4 and (can be ignored)
NMI on pin 6 (cannot be ignored)

If the signal on pin 6 falls from high voltage to low voltage the CPU will perform a call to the non-maskable-interrupt handler.
It will read the contents of address $FFFE and jump to the 16-bit location contained in that address.
After it's done it will return to where execution was before and resume operation as if nothing happened.

In the interrupt handler the CPU will query its peripherals to find out which one generated the interrupt.
Usually a specific chip is connected to the interrupt pin and that chip can be queried using an INput/OUTput instruction to get the relevant info quickly. On the c64 the CIA 6526 was used.

Are there specific areas of the CPU that contain addresses for handlers registered by the OS?

You set up the CPU so that it calls a predetermined address when it receives an interrupt.
In early CPU's this address has hardcoded in the chip. In newer chips the system kernel can change the interrupt address using a privileged instruction.

On modern processors this works the same but things are complicated because everything is virtualised.

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  • $\begingroup$ "After it's done it will return to where execution was before" - actually the software does that. The CPU does not do that automatically. $\endgroup$
    – user253751
    Jan 20, 2020 at 12:31
  • $\begingroup$ What about saving the current context and restoring later $\endgroup$
    – Sourav Kannantha B
    Sep 15 at 9:48
  • $\begingroup$ @SouravKannanthaB, that is up to the code in the interrupt handler. When the interrupt jumps to that code, it pushes its return address on the stack (or in some special register, it depends per CPU architecture). And it is up to the interrupt code to make sure all data is restored, before the code exits the interrupt. $\endgroup$
    – Johan
    Sep 17 at 16:09

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