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NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction will propagate through the pipeline with no effect. There is no data path defined for a jump that tells the processor to change the PC. The only thing that changes the PC (aside from the normal PC+4) is a beq.


I'm learning about MIPS pipelining and stages, but what is excruciatingly unclear is how a jump instruction is executed. On an assignment question, I'm asked to trace the pipeline with the command "j 16", but there does not appear to be any details about how the logic is handled. The closest thing I can find of any relevance is to do with beq, but the opcodes are different... beq is 000100 and j is 000010. The following table outlines how the control codes work for four classes of opcodes, but it doesn't explain what happens for jump, and subsequently, how the machine knows to jump and what it does with the command...

Datapath diagram with control registers Opcode-Control Codes

So, if I have the instruction 000010 00000000000000000000000100, how does this get handled by the data path?

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  • $\begingroup$ You are correct that j (jump) is similar to beq (branch on equal). The difference is what comes back to input 1 of the mux at the front of the instruction fetch stage, and what comes back as the control of that mux. Those two signals are coming from the Mem stage. So you need to figure out how to control the adder and ALU in the execute stage to make sure that you get the correct destination address coming from the adder, and the right signal coming from the ALU to make sure that the "Branch" And gate in the Mem stage always sends a "1" to the Mux at the front of the IF stage. $\endgroup$ – Wandering Logic Jan 30 '14 at 12:41
  • $\begingroup$ That doesn't seem to make any sense, though... A jump is supposed to be able to go anywhere in memory, but a beq can only jump forward. If the jump instruction went through the adder then the address would be added to the current PC. Additionally, my text says "The jump instruction operates by replacing the lower 28 bits of the PC with the lower 26 bits of the instruction shifted left by 2 bits." But it doesn't elaborate beyond that. I don't know if this diagram is missing information or if it's just not explained properly. $\endgroup$ – agent154 Jan 30 '14 at 14:45
  • $\begingroup$ You are right that you will need to add various control and data paths to the diagram to implement the jump. (Not related to your original question but beq actually can jump backwards, the lower input of the adder is sign extended (in the register stage.)) $\endgroup$ – Wandering Logic Jan 30 '14 at 20:51
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    $\begingroup$ Also, there may be a diagram with the added control and data for jump in some figure a few pages later. I don't have my copy of Patterson and Hennessy handy (and probably have a different edition than you anyway) so there may not be, but I thought I remembered them building that diagram further. $\endgroup$ – Wandering Logic Jan 30 '14 at 20:54
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You are correct. The above data path doesn't have the parts that support jump instruction. Yet, those are easy to add.

The pipelined datapath in your question is based on a single-cycle MIPS that doesn't support jumps (Figure 5.21 in Patterson and Hennessy). In order to add jump support, consider the single-cycle MIPS datapath of Figure 5.24; then add the jump parts to the pipelined architecture.

However, note that jumps and branches must be treated correctly in order to avoid control hazards - specifically, new instructions that entered the pipe after the jump should not be executed. The complete datapath that takes care of control hazards (again, for branches only) appears in Figure 6.41.

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