Branch instructions in MIPS have a 16-bit offset value which is sign-extended to provide offsets between -32768 and 32767 words (-131072 and 131068 bytes). This offset is added to the Next PC value rather than the PC of the branch itself.
Why the NPC is used rather than the PC of the branch is not obvious (to me). This may have been related to the use in the Stanford MIPS project of an assembler which performed the limited instruction reordering for filling the delayed branch slot with a previous instruction. With such a design, the offset for forward branches (i.e., branches with positive offsets, commonly used to implement if-then, conditionally branching over the then clause) would never be changed during the conversion and the offset for backward branches (i.e., branches with negative offsets, commonly used for loops) would only be changed when the delay slot had to be filled with an extra no-op instruction. This might simplify compiler development.
An alternative speculation would be that such slightly simplified the initial implementation where the branch was evaluated in the second pipeline stage when the current PC is the NPC relative to the branch instruction.
A third speculation is that such was considered conceptually cleaner given the use of a delayed branch slot. The offset then becomes relative to the instruction in which the branch is "activated".