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will you recommend use of branch prediction buffers for 5 stage integer MIPS pipeline. Does this increase the efficiency or not?

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closed as unclear what you're asking by Yuval Filmus, Juho, Rick Decker, David Richerby, Luke Mathieson Feb 22 '14 at 8:32

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Given a scalar 5-stage pipeline with a branch delay slot (and branch resolution in the decode stage) like the MIPS R2000, branch prediction would have almost no benefit since a branch would usually be resolved before the next instruction address is needed. This simple pipeline also has no support of speculative execution or fetching ahead. (A branch predictor might improve performance for such a simple pipeline if the branch could not be resolved in the decode stage because the dependent data was not yet available, e.g., a data cache miss, and the branch target was an instruction cache miss. In that uncommon case, a branch predictor would allow prefetching of the branch target.)

A simple 5-stage pipeline without a branch delay slot or with the branch direction or target resolved in the execute stage (rather than in the decode stage) could benefit from branch prediction. If the front-end of the pipeline was decoupled from the back-end of the pipeline (buffering instructions to allow the front-end to fetch ahead), then branch prediction would allow the buffer to be kept full which would then allow some latency in instruction cache misses to be hidden.

It might also be possible to use index and way prediction to keep the instruction cache access latency down to one cycle (i.e., without such branch prediction instruction fetch would be two cycles making a 6-stage pipeline) while increasing associativity and perhaps size (with associated increase in hit rate); but such complexity would probably not be worthwhile for such an otherwise simple design.

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