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Why are instruction decoding and register read are combined in single stage of a 5-stage MIPS-pipeline, even though they serve two different operation?

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  • $\begingroup$ This is about the implementation details of a specific processor which is not a computer scienece problem per se. Once you learn the reasons for the design decision maybe you can modify your question to ask for scientific reasons (if any exist)? $\endgroup$ – Raphael Feb 25 '14 at 20:25
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    $\begingroup$ @Raphael I beg to differ. “What stage are ID and RR at?” isn't computer science, but “Why are they combined?” is: it touches on general processor design principles. $\endgroup$ – Gilles Feb 25 '14 at 21:03
  • $\begingroup$ @Gilles I thought that might be the case, but I'd like to see a more meaty question then. All stages combine multiple operations, after all. $\endgroup$ – Raphael Feb 26 '14 at 6:59
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Instruction Decode and Register Read are done in parallel on that stage in order to prevent needing to wait on either to complete. There's no reason not to do this since they are both known at that point in time for the MIPS-Pipeline, and since they will most likely be needed for the next step (Execution Cycle).

By "no reason", I mean that you would effectively be using more power while separating them (as mentioned in the comments below). You would also be adding a whole extra stage in that case, as the stage before (Instruction Fetch) is what actually gets the information for ID and RR, and adding it to the stage after would not work because that stage requires both. Thus the only way to do it would be to add the stage in-between the ID stage and EX stage, which would add a whole extra cycle to every operation, which would obviously result in slow downs overall.

If you're interested in reading more about this, I'd recommend this textbook I'm using for a class (Computer Architecture: A Quantitative Approach by John Hennessy and David Patterson). It's got a pretty handy reference for MIPS especially from what I've read so far and it's where I pulled this information from.

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  • $\begingroup$ It won't surprise you to learn that Hennessy is one of the founders of MIPS Computer Systems. It doesn't get any more definitive than this. $\endgroup$ – Pseudonym Feb 23 '14 at 10:06
  • $\begingroup$ Delaying register read a little bit to determine which register name fields are actually used by the instruction can save energy. Expanding on "no reason" (reg. name extraction independent of opcode, reads are not destructive) would be good. MIPS R2000 also included branch resolution (compare registers equal/check register sign bit) in the decode stage allowing a single delay slot to fully avoid branch penalties; this requires register values. The R4000 (8-stage pipeline) docs call this stage Register Fetch (still contained decode; also had Icache hit determination). $\endgroup$ – Paul A. Clayton Feb 23 '14 at 14:04
  • $\begingroup$ Went ahead and expanded on the "no reason", see edits above. $\endgroup$ – GEMISIS Feb 23 '14 at 17:00

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