Given below are 3 different pipelined processors:
$P_1:\ 4\ stages\ with\ delays\ \ \ \ 0.6_{ms}\ \ 0.8_{ms}\ \ 0.6_{ms}\ \ 1.1_{ms}\\ P_2:\ 4\ stages\ with\ delays\ \ \ \ 2.0_{ms}\ \ 1.8_{ms}\ \ 2.0_{ms}\ \ 1.0_{ms}\\ P_3:\ 5\ stages\ with\ delays\ \ \ \ 1.0_{ms}\ \ 0.8_{ms}\ \ 1.0_{ms}\ \ 1.5_{ms}\ \ 1.5_{ms}$
One has to find the Peak Clock Frequencies of each $\mathbf{P_i}$. Pipeline buffer register latency is Zero.
I don't know how to solve this, but I've come up with an intuitive formula for calculating peak frequency of clock for processor $P_i$ as $$\mathcal{C_{p.f}}=\frac{1}{max(d_i)}$$ where $d_i$ is individual stage delay for processor $P_i$. For example for $P_2$ it's $\frac{1}{2}KHz = 0.5 KHz$.
Now I don't know whether it's the correct way to calculate peak frequency.
If it's not, can anyone tell me what is it?
P.S: I also don't know whether this is the right place to ask this question.
But I didn't have any idea about where to post it otherwise.
