Whatever you do, computing the next state for a cellular automaton ask for as many computation than there are cells in the automaton. Thus to get a constant time, you need as many computing core as there are cells.
The number of these in GPU are currently at most a few thousands, while the computation of the next state is so simple that I expect the result to be IO bound, i.e. you can get a very good approximation of the time needed by just considering the data movement needed (and if it isn't a good approximation, either the implementation has an inefficiency or the architecture isn't suitable, but that would be very surprising).
For FPGA, the question is more difficult and will probably depend on the mix of memory and computation units available. If I'm not too far out, you won't have enough memory to keep all units busy and if you rely on external memory, you are in the same seat as GPU, memory bandwidth will be the limiting factor and I'd not be surprised if the conclusion is that there is no advantage over GPU. (Note that while I've worked with FPGA, it was years ago, there may now be FPGA models with a right mix).
ASIC offers more flexibility. You can easily have a systolic like implementation (but with bidirectional data flow, some systolic is usually restricted to unidirectional data flow), each physical cell is one logical one: bit of memory and the needed logic to compute it's next state and is layed out so that it's physical neighbor are it's logical one. You are obviously in constant time realm. Depending on which hard macros you have, you may be better to be a little less obvious and have physical cells which regroup several logical one. The goal is to maximize what is done in one chip, in other word to minimize the communication with the outside of the chip as as soon as your communication needs are proportional to the number of cells, you'll be bandwidth limited. Yes, that mean that if you need to look at all the cells for each step, you are probably not a lot better than with GPU. (Full custom would provide only better integration, i.e. more cells per chip).
- if you want to look at all the intermediate states, GPU is the most effective approach
- if you don't, you need the volume to justify an ASIC to have something better, FPGA probably won't offer enough advantage if they have any.