# Moore's law and Clock Speed

This figure says according to moore's law number of transistors doubles about two years. but clock speed, power flattening after given stage. can anyone describe the reasons this flattening in clock-speed. Why can't we increase the clock speed more and more?

• Multi-core processors can lead to increase in other factors, while maintaining the clock speed. Commented Jun 20, 2014 at 16:50
• this figure only consider uniprocessor. isn't it? Commented Jun 20, 2014 at 16:52
• Is your question, "What factors influence the flattening of the Clock Speed and Power curves in this chart?" If so, this question is almost certainly better suited to a more hardware- or physics-oriented site as, in my understanding, all such factors are physical in nature (i.e., manufacturing constraints, heat, leakage, efficiency, etc.) Commented Jun 20, 2014 at 16:53
• "this figure only consider uniprocessor. isn't it?" Depends on what you mean by "uniprocessor". Notice that the dual-core Itanium 2 is plotted, for instance. Commented Jun 20, 2014 at 16:53
• Can you please edit the question to state the question more precisely? For one thing, there is no question in the body (merely some statements), which forces us to infer what you want an answer to. Spending some time to figure out exactly what your question is will help us help you more effectively, and increase the likelihood that you get a good answer.
– D.W.
Commented Jun 20, 2014 at 19:37

Here is a link to a similar discussion in another stack exchange where the causes are explained.

There are two different "laws" being graphed here, Moore's law, and Dennard scaling. Moore's law is an economic observation, made by Gordon Moore in 1965, that predicts that the number of transistors on a die will tend to double about every two years. It does not seem to be slowing down (yet). While there are reasons to believe that transistors will stop scaling down soon (14nm is 140 Angstroms (about the width of 140 hydrogen atoms)) it may be possible to continue Moore's law scaling for some time, either by making bigger chips (what Moore originally predicted) or by stacking multiple layers of transistors in the 3rd dimension.

Dennard Scaling, on the other hand, is an observation, made by Robert Dennard in 1974 that every time you scale down the width of a CMOS gate by a factor of 2, you can reduce both supply voltage and the threshold voltage by a factor of 2, the clock frequency can improve by a factor of 2, and the power density will stay constant. (Or you can scale down the voltage by less than 2, and you'll get a better than 2x clock frequency boost, but an increase in power.) When Dennard's observation was made a CMOS transistor was about 5 micron = 5000 nm wide. (So we've scaled transistor widths by a factor of about 360 in about 40 years.)

The limit that showed up in the early 2000s has to do with threshold voltage. Clock frequency (at a particular transistor size) is at best proportional to $V_{dd} - V_{th}$ (supply voltage minus threshold voltage), but as you scale $V_{th}$ down leakage current (and power) increases exponentially. That was fine from 1974 to about 2000 because $V_{dd}$ was much larger than $V_{th}$. (In 1974 $V_{dd}$ was usually about 12V.) So we could hold $V_{th}$ at around a volt or so, and just change $V_{dd}$. But now with $V_{dd}$ around 1.3V and $V_{th}$ around .5V, we can't scale voltage much anymore (without dramatically increasing leakage power.)

• all peripherally relevant but the question was also on CPU/clock speed. not sure how that relates to "performance". it would be good if you define "performance"
– vzn
Commented Jun 20, 2014 at 18:42
• Fixed. It now says "clock frequency" everywhere it should say "clock frequency." Commented Jun 20, 2014 at 19:10
• And it's not just transistors, wire delay has also hit constraints.
– user4577
Commented Jun 20, 2014 at 21:39

the topic of semiconductor scaling is very complex and multidimensional but basically, performance gains in clock speed could come with increased power applied to the chip. but when the gate widths and gate densities get very small (which is not graphed above but is roughly closely related to gate counts which is graphed) the power dissipation (heat) is much more challenging. essentially there is a ceiling where heat cannot be removed any more effectively or faster from the chip except with very expensive and increasingly impractical (unviable) systems eg liquid cooling. some of this heat is due to the following current leakage issue into the chip at a certain gate width reached mid 2000s:

This expanded version of Moore’s law held true into the mid-2000s, at which point the power consumption and clock speed improvements collapsed. The problem at 90nm was that transistor gates became too thin to prevent current from leaking out into the substrate.

the quote comes from this basic summary of the issues: