2
$\begingroup$

I read that a supercalar processor has redundant functional units. One can read this e.g. on Wikipedia.

How do such redundant units work?

Is a complex instruction (for accelerating heavy process, for example Instructions used in Intel IPP, Integrated Performance Primitives) decomposed in micro operations befaure being dispatched among these redudant functional units?

What about hardware instructions? Like AES-NI?

I also read the Wikipedia article SMT and did not understand the following sentence:

Superscalar means executing multiple instructions at the same time while thread-level parallelism (TLP) executes instructions from multiple threads within one processor chip at the same time.

I don't understand very well the distinction between these two things. Can somebody explain the subtleties?

$\endgroup$
  • 1
    $\begingroup$ It is not the case that superscalar processors have "redundant" functional units. Some (not all) have several functional units that are capable of performing the same function at the same time. $\endgroup$ – Wandering Logic Jul 3 '14 at 13:04
  • 1
    $\begingroup$ The wikipedia page is wrong. They use the term "redundant" where they mean "more than one." $\endgroup$ – Wandering Logic Jul 3 '14 at 13:12
  • 1
    $\begingroup$ No. Google the definition of "redundant." It means "not or no longer needed or useful; superfluous," or "not strictly necessary to functioning but included in case of failure in another component". $\endgroup$ – Wandering Logic Jul 3 '14 at 13:17
  • 2
    $\begingroup$ A superscalar processor has more than one functional unit. But the functional units may perform different functions. For example, often there is an arithmetic unit, a memory unit and a branching unit. You can't do a division operation with a memory unit, but the processor can simultaneously execute a division operation and a memory load operation. $\endgroup$ – Wandering Logic Jul 3 '14 at 13:20
  • 2
    $\begingroup$ You are asking multiple things at once. Please restrict your post to a single question! $\endgroup$ – Raphael Jul 3 '14 at 14:51
2
$\begingroup$

You should understand that any program is a sequence of instructions (ok, you an think of it as a collection of threads, where every thread is a sequence of instructions or a virtual process that executes that series of instructions). The instructions are supposed to be executed one after another. Single pipeline processor fetches instruction as they are ought to, every clock cycle and keeps its functional unit executing an instruction per cycle. This is not very true actually because execution takes multiple cycles and you fetch next instruction before previous is complete. But we pretend that instructions are still executed one after another and you still need one FU. Superscalars, however, cheat. They tell to the user that they still execute her program as designed, one instruction after another, yet take a window of neighbor instructions and execute them at once. They introduce extra FUs (Wikipedia called them "redundant") for this technique, called "Instruction Level Parallelism" (ILP).

Superscalars also have to entail a complex dependency detection and maintenance mechanism. As Amdahl has explained), because instructions of the same thread operate on the same data set, you have a lot of dependencies, especially among neighbor instructions and, thus cannot gain a lot of parallelism at ILP. The parallel pipelines are therefore sometimes used to execute different threads. This is full-scale parallelism already (except the synchronization cases and cache contention, which prevents any advantage of TLP over ILP, especially if von Neumann bottleneck is considered). Such TLP is known as hyperthreading. Yet, it is true parallelism since now threads are indeed executed in parallel, as if there are multiple cores, rather than parallelism is emulated by periodically switching threads on a single pipeline and, therefore, is also called "simultaneous multithreading".

I do not even see any reason to differentiate between multicore and hyperthreading. Since different pipelines execute different threads, this means that they have separate instruction pointer, set of registers and everything you need for the context, which are switched. Might be the common cache and shared FUs is the only things that distinguishes single core from multiple cores. Yes, shared cache. This may save you from cache incoherence /memory consistence problems that can happen in truly multicore system.

$\endgroup$
  • $\begingroup$ Thanks but I am sceptic. You write "I do not even see any reason to differentiate between multicore and hyperthreading". Really ?? In general applications have only a small gain by using hyperthreading, so I'm wondering if instructions belonging to one thread can be dispatched in redundant functional units... This would coincide with the general low gain of hyperthreading. $\endgroup$ – user7060 Jul 4 '14 at 13:52
  • $\begingroup$ "Since different pipelines execute different threads, this means that they have separate instruction pointer, set of registers and everything you need for the context, which are switched." I've seen this post cs.stackexchange.com/questions/11426/… $\endgroup$ – user7060 Jul 4 '14 at 14:01
  • $\begingroup$ That post is about multicores. Multicores share main memory and large slow cache, eg. L3 or something. Reduntant FUs are exactly for different pipelines could use them. I do not see how redundancy of FUs can slow down your system. The data flow dependency among instructions certainly does. $\endgroup$ – Val Jul 4 '14 at 14:25
  • $\begingroup$ I don't undserstand and I think we make a complete digression. My question is about a citation from Wiki, which lask of details. For instance "within one processor chip at the same time" is not sufficiently accurate for me... $\endgroup$ – user7060 Jul 4 '14 at 22:44
  • $\begingroup$ "Superscalar" stands for multiple instructions at once by the parallel pipelines of same core. It either means ILP or TLP. You can also do TLP employing multi(core)processor within single chip or even distribute it over several chips. You cannot distribute ILP over multiple chips (well, you can but it would not worth the effect). $\endgroup$ – Val Jul 5 '14 at 9:14

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.