This a problem in a computer architecture course that's giving me some trouble:
You have an application whose memory access pattern is a stream and its entire data set is 128kB. The data cache in your machine has a capacity of 64kB. It is word-addressable and direct-mapped with 32B lines. It is able to fetch one line at a time.
Given the access pattern: 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, …, 32768, where each access is a 4B word.
- What is the miss rate?
- Can the miss rate be reduced by using a larger cache?
- Can the miss rate be reduced if the size of the data set were reduced?
Here's what I think is going on: The cache is initially empty, meaning each access will result in a compulsory miss. So would this mean the miss rate is 100%, since no data is initially loaded and the pattern doesn't hit any address twice?
Any help understanding this would be much appreciated!