# Calculating miss rates of word-addressable and direct-mapped cache

This a problem in a computer architecture course that's giving me some trouble:

You have an application whose memory access pattern is a stream and its entire data set is 128kB. The data cache in your machine has a capacity of 64kB. It is word-addressable and direct-mapped with 32B lines. It is able to fetch one line at a time.

Given the access pattern: 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, …, 32768, where each access is a 4B word.

1. What is the miss rate?
2. Can the miss rate be reduced by using a larger cache?
3. Can the miss rate be reduced if the size of the data set were reduced?

Here's what I think is going on: The cache is initially empty, meaning each access will result in a compulsory miss. So would this mean the miss rate is 100%, since no data is initially loaded and the pattern doesn't hit any address twice?

Any help understanding this would be much appreciated!

• The reason why cache works is the principle of locality. It depends how data is loaded into the cache I think, if it's only loaded once the address is accessed, yes that will result in 100% miss rate. However, it can be possible to fetch more data (When position Y is needed, load position Y + position Y+ 1, because you guess the other positions are needed soon.) If I recall correctly, for hard-drives they fetch more data than the data requested, because the PoL holds, the next request could be in cache. Not sure how applicable this is to your situation. Jul 6, 2014 at 21:43
• Thanks Dylan. I was missing that critical piece of the puzzle. Jul 6, 2014 at 22:26