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This is am example of a RAM address in the MIPS architecture (32 bits)

enter image description here

I can imagine the RAM as having 32 pins just to inform the RAM address I want to access, so I can access each of these words in the image (because I saw in this vídeo). I think, then, it should need another 32 pins to inform what's the word in that address, just like in the vídeo. I don't know, however, how the CPU could support 2 different 32 pins bus (but this is another problem).

What I don't understand, for real, is why I need and offset in the instruction "load word", if I can only access one address at the time! What if I say "load word", give the address number 2, and then say na offset of 4? It will load part of the word from the address 2, and part from the address 3? How is this possible?

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First of all, to short circuit your question, I must say that you can not ready from multiple memory locations at the same time in the MIPS architecture.

Second, your interpretation of the offset is wrong. You assumed the offset is a bit offset, while it's actually an offset in bytes. Meaning if you give the address 2 and offset 4, the memory location to be read from will be 6 (2+4).

Third, more details into the MIPS lw (load word) instruction. The syntax is as follow: lw \$d, off(\$r), where \$d is the destination register (where the word is loaded to), off is an immediate 32 bit constant and \$r is your base register. What happens is as follow:

  1. The target ram address is calculated by adding off and the value in \$r.
  2. The calculated address in loaded in the memory register
  3. The control unit enabled the RAM to get the value at the address
  4. The value is set to the \$d register

Fourth, something I haven't mentioned before, related to the addressing pattern of the ram. As you may know, the ram stores bytes, no actual words. What's the problem you may wonder? It's something called word alignment, and it's the reason why you couldn't load a word from address 6. A word is a 4 byte value, and for fast design purposes, when loading a word, the address has to be a multiple of 4. I won't go in the design details, but suffice to say that this permits greater memory transfer speed than allowing any address.

What this means is that when loading and storing words, you have to respect the word boundaries. If you try to read from a bad memory location i.e. not a multiple of 4, e.g. 6, you will have a memory exception; meaning you program likely crashes.

In practice, this mean that if you have to store tree words a,b and c, you could store them at address 0x01234560, 0x01234564 and 0x01234568.

EXTRA: why use an offset

So, in my last example, you might have noticed my words were close in memory, but i didn't start at 0x00000000. Actually, the first word starts at adress 0x01234560. Here's how you can take that into consideration with the lw syntax.

  1. First, set the value of \$r to 0x01234560
  2. Then, to load a, you write lw \$d, 0(\$r). The will load the value at 0+\$r, 0 + 0x01234560 = 0x01234560
  3. Then, to load b, you write lw \$d, 4(\$r). The will load the value at 4+\$r, 4 + 0x01234560 = 0x01234564
  4. Then, to load c, you write lw \$d, 8(\$r). The will load the value at 8+\$r, 8 + 0x01234560 = 0x01234568

I hope this completely answers your question. The only thing I haven't touched is why you'd end up at such complex memory locations. Short answer: it's due to the structure of the compiled program and the way it's loaded into memory. I suggest you look further into that before delving deeper into the world of computer electronics. A sound knowledge of the structure of a program will greatly help understand why the CPU and instruction set were made that way.

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  • $\begingroup$ But if the RAM stores bytes, it means that the control UNIT is getting access to 4 bytes at one time. How is this possible? $\endgroup$ – Revering Sumoda Aug 7 '14 at 19:30
  • $\begingroup$ The control unit is designed to handle words of 4 bytes in MIPS. Don't forget that the video presents the scotts cpu, not MIPS. Also, to allow this, the ram has 32 lines coming out of it (instead of 8). To allow an output of 32 bytes. For this to work, the RAM has to store the bytes in rows of 4 instead of individually. This is one of the reason behind the alignment mentioned in the answer. If this answers your question, don't forget to accept it. $\endgroup$ – ZeroUltimax Aug 8 '14 at 1:11
  • $\begingroup$ Thank you SO MUCH, your answer is clear and simples! By the way: in the video, there are wires going to the RAM, and coming from the RAM. It looks like the computer have 2 bus's going to the CPU. How it Works in MIPS architecture? I assume there's only one bus, and it its 32bit wide. $\endgroup$ – Revering Sumoda Aug 8 '14 at 4:28
  • $\begingroup$ There is at least two buses. If you look around 15:50, it talks of memory addresses. There's one bus for the address (out of memory register) and one for data. On 32 bit mips, both would have 32 bits. As you know, there's two basic operations possible with the ram, set or enable. For set, the address bus tells the RAM which address to save to, and the data bus has the data on it from whatever register is enabled. For enable, the address tells the RAM what address it wants the data from, and the data bus reports the data to any register being set. Same as scotts, with 32 bits in and out of it. $\endgroup$ – ZeroUltimax Aug 8 '14 at 17:42

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