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From my understanding(correct me if I am wrong) when I read data from RAM memory it is copied into processor cache and than it is copied into register to be used by the processor. When I create data (like variable) is it first created in register and than copied to cache and from cache to RAM or is it directly created in RAM?

Additional question:Does stack and heap exist only in RAM or do they exist in processor cache as well?

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    $\begingroup$ What do you mean by "create data"? Some (temporary) data never makes it to cache let alone memory! $\endgroup$ – Raphael Aug 8 '14 at 7:00
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When you read data from a given memory address, the memory manager checks if there is a copy in the cache. If yes (cache hit), the copy is read into the register. If no (cache miss), the cache is first updated with a row of memory from RAM; then the data can be read into the register.

Conversely, when you write to a memory address, the data is just written to the cache, making room if required. Later, when the cache line must be freed or is explicitly flushed, the row of memory is copied to RAM.

If you perform successive reads and writes to the same address, it can very well arise that all changes are made in the cache and the RAM left untouched. From the processor's point of view, the presence of the cache is transparent. It just reads from and writes to memory addresses, and the memory manager optimizes the transfers.

Note that you don't "create" data in memory. When a program is loaded, some RAM space is assigned to it and reserved (possibly also initialized), and the addresses of the variables are "mapped" onto that space. Then the program is allowed to write to or read from these addresses.

In modern, multicore CPUs, cache management is much more complicated because several concurrent reads/writes to the same memory addresses can occur. The MMU must ensure that all caches and RAM remain coherent and "synchronize" their content.

The stack and the heap have a range of memory addresses allocated, and they are handled through the cache like ordinary program space. The stack is an essential resource during program execution and it is extremely frequently accessed. It is important that it be cached as well.

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  • $\begingroup$ "If no (cache miss), the cache is first updated with a row of memory from RAM". This is a bit misleading. The cache is updated with a row from wherever the data happens to be, which may or may not be RAM. (For example, it's often in another cache.) $\endgroup$ – David Schwartz Aug 7 '14 at 23:49
  • $\begingroup$ @David: I don't get your point. We are discussing a single level cache model. $\endgroup$ – Yves Daoust Aug 8 '14 at 0:09
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    $\begingroup$ It doesn't matter how many levels of cache you have. You can have but one level of cache and still have cache coherency between sibling caches at the same level. If we're going to imagine some hypothetical system with just one cache, I suppose you can imagine it has any properties you wish. But there's not much point in discussing a system that has little resemblance to the real world systems the question is (presumably) asking about. $\endgroup$ – David Schwartz Aug 8 '14 at 0:19
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    $\begingroup$ I wrote "In modern, multicore CPUs, cache management is much more complicated...". It is premature to overflow the OP with extra info when his question is about the basics. $\endgroup$ – Yves Daoust Aug 8 '14 at 6:18
  • $\begingroup$ I agree that it's important to avoid extra info, but the info you do provide must be correct. Simplifying is fine, but simplifying incorrectly is not. The fix is trivial and doesn't make your explanation more complicated. For example, you could just change "If no (cache miss), the cache is first updated with a row of memory from RAM" to "If no (cache miss), the row of data is first loaded into the cache". $\endgroup$ – David Schwartz Aug 8 '14 at 6:25
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From my understanding(correct me if I am wrong) when I read data from RAM memory it is copied into processor cache and than it is copied into register to be used by the processor.

That is generally correct. Just be sure you understand that we're talking about reading data that happens to be in RAM. We're not talking about issuing an instruction to read data from an address because that data may, or may not, be in RAM. (It may be in this core's cache, it may be in some other core's cache, it may be on a peripheral, and so on.)

When I create data (like variable) is it first created in register and than copied to cache and from cache to RAM or is it directly created in RAM?

Yes (though the register can by bypassed on most processors), but again, let's be clear. We're talking about what happens if, for some reason, the data does in fact need to go to RAM. Writing to an address may or may not wind up writing data to RAM.

Additional question:Does stack and heap exist only in RAM or do they exist in processor cache as well?

Forcing stack and heap operations to go to RAM would make performance horrible. Stacks and heaps are used constantly, and we want to avoid using RAM wherever possible. The point of the cache is to avoid RAM operations as much as we possibly can. Not improving the most common operations would be a non-starter.

Basically, the distinction between stack and heap is primarily in how the address space is used by the instructions. As far as the cache and memory hardware is concerned, they're both just address space that is ultimately backed by RAM.

The primary purpose of all of these caches is essentially to minimize the number of reads and writes that have to go to RAM. Even if a core isn't waiting for the reads and writes to complete, memory bandwidth is typically a very limited resource compared to the rate at which CPUs can process information.

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