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I've been coming across a problem in one of my assignments requiring the calculation of the speedup of a two-way superscalar cpu. The problem is as follows:

There is a two-way superscalar CPU with 2 pipelines U & V. The instruction pipeline U processes the complex instructions, while the instruction pipeline V processes the simple instructions. The ratio of the processing times in the phases of pipelines U and V is 3:1. I'm required to calculate the processing time for 1000 instructions in GPSS (General Purpose Simulation System) - Student Version, for the following cases:

50% complex and 50% simple instructions
25% complex and 75% simple instructions
75% complex and 25% simple instructions
Probability of 50% complex and 50% simple instructions
Probability of 25% complex and 75% simple instructions
Probability of 75% complex and 25% simple instructions

I have the simulation files and i can deduce the execution time for each case T(Supuperscalar).

However I'm stuck with the requirement of finding the speedup for each case.

I'm aware that the speed up can be calculated as Speedup = T(Sequential)/T(superscalar) = k*n/k+(n-1) where k is the number of stages and n is instruction number, however I'm having a hard time figuring out how to calculate the sequential time for the above cases.

I would really appreciate if somebody can give me a hint here.

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The speedup is the ratio of the time when using your superscalar CPU, divided by the time if you used a simple sequential CPU. For the sequential CPU, imagine that at each step you can execute either pipeline U or pipeline V, but not both at the same time. Simulate the workload on that kind of sequential CPU, and see what the execution time would be.

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The quick answer to your question is that you should simulate the program with 1k instructions you have. In the case of non-super-scalar, make sure that you can process either one complex or one simple instruction at a time. Not both, exactly as D.W mentioned above. Then you will compute the ratio of the number of cycles taken to complete 1k instructions in each scenario.

Nevertheless, I think I need to note the followings in your question:

  • Having a factor of 2 super-scalar, but allowing each of the 2 differs in cycle to complete an instruction will make things very hard to manage.
  • Saying that your architecture has 2 pipelines U and V to process instructions are very strange. If your CPU can simultaneously process 2 instructions and complete 2 instructions in the same cycle, then it has a superscalar factor of 2.
  • The number of pipelines is used to describe the number of stages that your machine instruction has. You can imagine that each stage is completed by a different circuitry area (pipeline) in the CPU, so the number of stages is actually the number of pipelines you have. Not as you asked.
  • You can't really have the speedup formula with n and k and superscalar factor because this depends on the instructions that you feed into the CPU. You have to actually simulate to know what the speedup ratio is.
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