"If so then what microarchitectual changes can be made to allow CPU to pipeline operations so that it can reach 1 operation per clock assuming all hits."
It seems you are confusing latency here with throughput. Many CPUs have two read and one write port, and can read two items and write one item in the same cycle. So I assume you are asking about one cycle latency. And this is a really interesting question, and the answer is: You can make your CPU really slow.
L1 cache doesn't have multi-cycle latency just for fun. Addressing data in a large cache takes time, and more time the bigger the cache is. You need more time to select the correct data, you need more time because you have tons of connections to all the different cache lines. The only way to get the number of cycles latency down is (a) reduce the clock speed and (b) reduce the size of the cache. Both are things that you don't want.