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Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not clear which ones these precisely are. Can someone elaborate on what "limited dual issue" exactly means ?

Further, came across another terminology around limited dual issue - asymmetric and symmetric. What does asymmetric limited dual issue mean ?

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    $\begingroup$ My guess (I have not looked it up and had not heard the term before) is that asymmetric limited dual issue does not have hardware to swap the position of the instructions, so if two instruction could otherwise issue in parallel but are in the wrong order in the instruction stream (e.g., if slot 0 handled ALU instructions and slot 1 branches and memory accesses, a load and add that were independent would only dual issue if the add was before the load in the instruction stream). Limited dual issues usually implies very limited (e.g., no GP dual issue CPUs support two || multiplies) $\endgroup$ – Paul A. Clayton Sep 5 '14 at 20:55
  • $\begingroup$ Thanks - that makes sense. So then all GP dual issue CPUs are limited dual issue ? Some online content does use the term "full dual issue" as well. It seems from your reply that the exact nature of "limited dual issue" will vary from one pipeline to another. Is this correct ? $\endgroup$ – user3901167 Sep 5 '14 at 21:32
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    $\begingroup$ Based on a reference in Embedded Systems: Hardware, Design and Implementation it looks like "asymmetric" means merely that not all issue slots have the same capabilities. This makes "limited" somewhat redundant since asymmetric issue slots necessarily limit issue potential. Generally dual issue would be considered "not limited" if there is not a substantial performance cost in 'typical' code, e.g., only one slot handling jumps/branches is not costly, implementation cost also seems to be a factor. $\endgroup$ – Paul A. Clayton Sep 6 '14 at 20:53

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