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I cannot find a to-the-point reference for my question. Am I correct in assuming that if you have an L1 and an L2 cache, typically the L2 cache linesize is larger?

For the following, let's assume a word size of 1 byte, an array 'a'of one byte words, an L2 cache with blocksize of 8 bytes, and an L1 cache of 4 bytes.

So, if you try to access an element a[2] in an array, given that both caches are cold, then a[0] - a[7] will be transferred to L2, and then a[0] - a[3] will be transferred to L1, and then a[2] can be sent to the register?

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    $\begingroup$ The L2 cache line must be at least as large as the L1 cache line, but in many cases (such as the current Intel Core series), the L1/L2 caches use the same sized cache line. There is a much more detailed explanation here: stackoverflow.com/questions/14707803/… $\endgroup$ – Ken P Sep 7 '14 at 22:12
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    $\begingroup$ Not all L2 caches use strict inclusion. AMD's Athlon L2 caches even used strict exclusion (i.e., L2 acted as a huge victim cache). It is not rare for outer levels of cache to use a larger line size, but recent x86 implementations seem to have chosen a single 64B line size for all levels (and do not use sectoring). $\endgroup$ – Paul A. Clayton Sep 8 '14 at 1:57
  • $\begingroup$ The title you have chosen is not well suited to representing your question. Please take some time to improve it; we have collected some advice here. Thank you! $\endgroup$ – Raphael Jun 3 '16 at 22:52
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The cache line size is 64 Bytes. The size of the last-level cache varies a lot: 4MB per 2 Cores for Intel Core2 processor QX6850 and Intel Xeon processor 5300 series, 6MB per 2 Cores for Intel Core2 processor QX9770 and Intel Xeon processor 5400 series, 8MB per 4 cores for Intel Core i7-965 and Intel Xeon processor 5500 series.

Source: Intel forums

You can also find few details here about Intel processors cache line size.

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    $\begingroup$ Thank you for your contribution. However, this doesn't appear to answer the question that was asked. As a reminder, the question asks whether typically the L2 cache linesize is larger than the L1 cache linesize. That's a yes-or-no question, so any answer should start by answering yes or no and then providing explanation and justification of the answer. I don't see that here. Also, we don't want to be just a link farm with links to external sites. Please see cs.stackexchange.com/help/how-to-answer and edit your answer. Thank you! $\endgroup$ – D.W. Jun 3 '16 at 19:14

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