# Question on SR latch functionality

Below is the diagram of SR latch

The following is the functional table as per my scrutiny .

Sl.no    S | R    Q(t) | Q'(t)    Q(t+1) | Q'(t+1)    Q(t+2) | Q'(t+2)   Q(t+3) | Q'(t+3)   Remark
=====   ===|===  ======|======    =======|=======    ========|========  ========|========= ========
1        0 | 0       0 | 0             1 | 1               0 | 0              1 | 1        Oscillaton
2        0 | 0       0 | 1             0 | 1               0 | 1              0 | 1        Stable(Hold)
3        0 | 0       1 | 0             1 | 0               1 | 0              1 | 0        Stable(Hold)
4        0 | 0       1 | 1             0 | 0               1 | 1              0 | 0        Oscillaton
5        0 | 1       0 | 0             0 | 1               0 | 1              0 | 1        Stable
6        0 | 1       0 | 1             0 | 1               0 | 1              0 | 1        Stable(Reset)
7        0 | 1       1 | 0             0 | 0               0 | 1              0 | 1        Stable-1(Reset)
8        0 | 1       1 | 1             0 | 0               0 | 1              0 | 1        Stable-1
9        1 | 0       0 | 0             1 | 0               1 | 0              1 | 0        Stable
10       1 | 0       0 | 1             0 | 0               1 | 0              1 | 0        Stable-1(Set)
11       1 | 0       1 | 0             1 | 0               1 | 0              1 | 0        Stable(Set)
12       1 | 0       1 | 1             0 | 0               1 | 0              1 | 0        Stable-1
13       1 | 1       0 | 0             0 | 0               0 | 0              0 | 0        Stable
14       1 | 1       0 | 1             0 | 0               0 | 0              0 | 0        Stable
15       1 | 1       1 | 0             0 | 0               0 | 0              0 | 0        Stable
16       1 | 1       1 | 1             0 | 0               0 | 0              0 | 0        Stable


Notation :

Stable : Stable output state

Stable-1 : Stable output state after one time unit delay

Set , Reset , Hold are as per normal usage.

My doubts :

1) If S=R=1 , output is stable and is 0,0 . Is this state undesirable or undefined or invalid ?

2) Why Q and Q' must always be complement to each other ? Is it necessary for the reason "to prevent oscillations in 1,4" ?

3) Suppose if we assume that we prevent S=R=1 and Q=Q' . But then in 7,10 why stable state(Set/Reset) not took place in next state itself ? Is this type of delay accepted ?

• 1) Please focus on one question per post. You overly generic question title clearly indicates that something is amiss. 2) This question may be better off on Electrical Engineering? – Raphael Sep 9 '14 at 10:11
• @Raphael 1)But all the 3 doubts i asked are related to one another . 2)And there is another question on SR latch cs.stackexchange.com/questions/10614/… . Is it also off-topic here ? – hanugm Sep 9 '14 at 10:22
• @hanu, questions about digital design are on-topic here. They are also on-topic at Electrical Engineering. You would probably get an answer at Electrical Engineering more quickly. – Wandering Logic Sep 9 '14 at 11:23
• But I am wondering why some one down-voted my question , which is not of type "Low standard" or "Do my home work" type . Is there any way to report these fake down-votes ? – hanugm Sep 9 '14 at 11:26
• Down votes are part of stack exchange. It is how other users encourage you to improve your question (or answer). In the case of this question someone (quite legitimately) felt that the question could be improved. For instance, @Raphael pointed out that your question title is way too generic and that you appear to ask three different questions (it may be the case that your questions are really three aspects of the same thing, but it is your responsibility to make that clear.) – Wandering Logic Sep 9 '14 at 12:07

The 0,0 state is undesirable for several reasons. The circuit that comes next may be relying on the invariant that Q' = not(Q). And, as you pointed out, it can lead to oscilations.