Somewhere on Internet I read : Whenever word size is greater than memory cell size, then there is a need for accessing multiple memory cell
Example:
for 16 bit processor:
MOV AX [2000]
To transfer memory content, we need to transfer 16 bit data , so we need to access 2 memory cells
M[2000 H]
&
M[2001 H]
But I didnt get this. Why 2 cells ?
I interpreted as follows:
1) 8 bit binary code will be fetched which decoded as MOV AX.
2) From next memory location , (00 H ) will be fetched as memory is byte addressable.
3) From next memory location , (20 H ) will be fetched.
4) In IR register it is treated as ( 2000 H ) and data at (2000 H) memory location is fetched and moved to AX register.
So why to access M[2001 H] memory location ??
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1$\begingroup$ Does this concern a specific processor? In that case, it's probably offtopic here. $\endgroup$– RaphaelCommented Sep 18, 2014 at 14:53
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2 Answers
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I am not sure if this is actually on-topic here, but anyway.
The main memory in x86 architectures is addressed byte-wise. If you want to retrieve 16 bits from address 2000h (note that AX is a 16 register), then you will need to read 8 bits from 2000h and 8 bits from 2001h. This is why the operation needs to read "2 cells". Note that the term "cell" is not the correct one, as it typically refers to individual 1-bit memory units without addressing logic.
Note that the processor actually doesn't read the two bytes separately. Rather, the content from bytes 2000h and 2001h are fetched at the same time as the data bus to cache and main memory is >8 bits and the addresses you have here as examples are aligned, so the underlying architecture supports the parallel read.
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$\begingroup$ I got your point.Thank you. But I got new info from your post i.e. parallel read. Do you have any video or link which will show how this parallel read happens ? Because I want to understand its Fetch-Decode-Execute cycle and to know , how many cycle this parallel read instruction will take. $\endgroup$ Commented Sep 18, 2014 at 9:22
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$\begingroup$ The term "parallel read" is probably misleading. It is a single read instruction of multiple consecutive well-aligned bytes. Most likely the Hennesy/Patterson book explains this in Section 2. How many cycles it takes is hardly predictable on modern CPUs, as it depends on whether the data is in the first or second level cache and whether branch prediction has led to pre-buffering of the data. In "good old times", the x86 reference manual of Intel listed numbers of clock cycles for some operations. Such numbers are almost meaningless today. $\endgroup$– DCTLibCommented Sep 18, 2014 at 11:24
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I am assuming that you are talking about an Intel 8088 CPU. In that case, the CPU is a 16-bit processor, but it only has an 8-bit data bus. The 8086 has a 16-bit data bus. When a MOV AX, [ADDR] is encountered, the CPU must initiate two bus cycles to read in all 16-bits. Since Intel machines are little endian, it must read in the low byte then the high byte. See my answer on endiness here. So with a memory address of 1600h, the low byte is in 1600h and is loaded into the AL portion of the register while the high byte is in 1601h and is loaded into the AH portion of the register.
On a 8086, only one bus cycle is used because that CPU reads the entire 16-bit word in one go.
So, from a hardware standpoint, when the MOV instruction is decoded, it looks at the source and destination operands. MOV AX, [2000h] (from your example) is interpreted as "copy contents of memory location 2000h into the AX register using 16-bits." The microcode inside the execution unit makes this interpretation and initiates two bus cycles (one on a 8086 for the reasons already given). Because the lower 8 bits of the address bus is multiplexed with the 8 bit data bus, the CPU has some control signals that enable the address to be de-multiplexed from the data.
There are other control signals that goes to a separate decoder chip that decodes the bus cycle into one of the following operations: *MEMR, *MEMW, *IOR, *IOW which are Memory Read, Memory Write, I/O Read, and I/O Write (The * indicates an active low signal which means that the signal line is active when a logic 0 is present.). The address is latched onto the bus for the duration of the cycle so the memory decoding logic can select which memory chips are to be enabled. It uses the high order bits of the address for this (bit x to bit 19). The lower bits are sent to the actual memory chips to select which cell to access (bits 0 to x). The read and write signals tell the memory chips if they should transmit the contents of the cell onto the data bus, or to take the data that is on the data bus and place it into the cell. In the case of a read, the memory chip transmits the data in the cell, either a 1 or 0 onto the data bus and to the CPU that is waiting for it.
When the bus cycle ends, the CPU takes whatever is on the data bus and loads it into the appropriate register. It does this entire operation twice to load a 16-bit value into a register. Then the instruction is complete and the CS:IP register pair is incremented to the next instruction to be executed.
