# Is the "data path cycle" the same thing of the "fetch-decode-execute cycle"?

I am reading the book Structured Computer Organization (5th edition) by Tanenbaum and at a certain point, in the second chapter, he talks about data path cycle and fetch-decode-execute cycle, and I am not understanding if they are really the same thing.

The data path cycle should be the number of small and minimal steps that a CPU goes through each cycle. On the other hand, the fetch-decode-execute cycle is the number of small steps that could be generalised like this:

1. Fetch the instruction from the memory and put it into a register
2. Change programming counter to point to the next instruction
3. Determine the type of the instruction fetched
4. If the instruction uses a word, determine where it is
5. Fetch the word, if needed, into a CPU register
6. Execute instruction
7. Go to step 1.

The fetch-decode-execute cycle is common to all computers, so each data path cycle should be a fetch-decode-execute cycle, right?

Data path cycle is not widely used terminology. I believe Tanenbaum made it up. I don't have the 5th edition, but if I look up Tanenbaum's slides on Google (for example: http://www.verlab.dcc.ufmg.br/_media/cursos/arquitetura/2011-1/transparencias/tanembaum_4.pdf) it appears that he is using data path cycle to refer to a single clock cycle. As in "the amount of time for all the signals to propagate all the way through the data path." Think of it as the amount of time required to perform one micro-instruction.

But Tanenbaum uses a multi-cycle-per-instruction microcoded organization, so the fetch-decode-execute cycle (for instructions rather than microinstructions) usually involves multiple clock cycles.

• From the term I would have guessed that it was the length of the critical path/loop between executing depend arithmetic operations (whereas the fetch-decode-execute cycle would apply to the control dependency of conditional branches evaluated in the execute cycle), which is close to what you indicate (and half-page 4 of the linked presentation indicates). Sep 21 '14 at 17:45
• Thanks. +1. (1) is it true that "a clock cycle == the time for executing a microinstruction"? If a micro instruction may finish in a shorter time than a clock cycle, then the next micro instruction has to wait till the next clock cycle starts? (2) Can I see "the fetch-decode-execute cycle" for an instruction as how an instruction consists of a sequence of microinstructions? "fetch" is done by running a micro instruction, "decode" is done by running a micro instruction, and "execute" is actually cpu running a micro instruction?
– Tim
Feb 12 '15 at 13:29
• (3) Given that a "instruction set" is also called a machine language, what is a "microinstruction set" called? A hardware language?
– Tim
Feb 12 '15 at 13:30
• @Wandering: In Tanenbaum's book, he mentions a data path cycle when introducing a register-register instruction (see part 2 of my post). Does your reply imply that a register-register instruction is a microinstruction? Is a register-memory instruction (also in the quote) also a microinstruction?
– Tim
Feb 20 '15 at 23:43
• @Tim in the quote he is talking about instructions not microinstructions. But in this case Tanenbaum seems to be using "data path cycle" to mean something slightly different from clock cycle. In this case he seems to be talking about the three steps (1) fetching operands, (2) computing results, (3) writing results to destination. Only in the simplest computers would all that happen in a single clock cycle. In most modern machines each of those would happen in a different pipeline stage. Feb 21 '15 at 3:16