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I'm studying the MIPS multi-cycle datapath, and I'm wondering what would happen if there was only one read port in the register file for certain instructions.

First, for R-type instructions, I know that it takes in 2 registers(for example, with 'add', rs and rt are both passed into read-port 1 and read-port 2 in the register file) and then added in the ALU. With only one read-port, the fetch step will be the same amount of time (fetching the instruction won't be affected), but the execution step will take 2 clock cycles instead of 1, because there will be a clock cycle for each time a register is passed in. Then, the other steps will also take the same amount of time after that.

But what about the load and store instructions? The register file takes rs and rt into the read-ports normally, but for example, sw STORES it's value in rt. Will this mean that the execution step won't be affected because rt will be passed into the "write register" port? Could anyone clear this up for me?

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For your MIPS CPU with 1read + 1write register file :

  • ALU instructions will last two cycles as you describe.
  • Load instructions can be executed in 1 cycle (with data in cache, etc...)
  • Store instructions must be split in two cycles to get the two source registers.

Another example, in SPARCs, STORE R1,[R2+R3] require two cycles with a 2R1W register bank, whereas LOAD [R1+R2],R3 can be executed in 1 cycle.

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    $\begingroup$ ALU instructions that use immediates only require one register read port. Furthermore, with result forwarding, a register value can be received from the forwarding network, further reducing the need for a second read port. Some out-of-order implementations (which are much more complex than the simple classic scalar RISC pipeline design) have used operand capture, which captures results on which an instruction is dependent while waiting for all operands to be available. $\endgroup$ – Paul A. Clayton Nov 27 '14 at 22:07
  • $\begingroup$ Ha ! Various optimisations are possible, for example the R0 register does not need to be read. For the simple MIPS CPU above, zeroing memory with 'SW R0,[R1+Imm]' can be done in 1 cycle... $\endgroup$ – TEMLIB Nov 28 '14 at 0:00

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