I am have a difficult time understanding when a direct map cache is a hit or a miss. My understanding is that when and index matches, but a tag doesn't it is still a miss but the new tag then takes over the previous tag on that index.

Address  Binary Address   Tag       Index   H/M

3        00000011        0000        011    Miss
180      10110100        1011        100    Miss
43       00101011        0010        011    Miss
2        00000010        0000        010    Miss
191      10111111        1011        111    Miss
88       01011000        0101        000    Miss
190      10111110        1011        110    Miss
14       00001110        0000        110    Miss
181      10110101        1011        101    Miss
44       00101100        0010        100    Miss
186      10111010        1011        010    Miss
253      11111101        1111        101    Miss

As such my theory is that all of the mappings are misses, am I correct?

Thank you so much guys!

  • The block size is one word; therefore we use no offset bit

  • The total size is 8 blocks; therefore we need only 3 index bits

  • $\begingroup$ The tag should be the 5 top bits, not just the top 4. Nonetheless, it looks like (assuming the cache starts out empty) you are correct that everything in the example is a miss. $\endgroup$ Commented Dec 7, 2014 at 13:15
  • $\begingroup$ Thank you @WanderingLogic, I really appreciate your help! Can you elaborate why the tag requires 5 bits as opposed to 4? Or when I change it in general? $\endgroup$ Commented Dec 7, 2014 at 13:44
  • $\begingroup$ @WanderingLogic Can you take a look at my caching hit/miss question? cs.stackexchange.com/questions/43235/… $\endgroup$ Commented Jun 4, 2015 at 16:01

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@Nathan: The binary address is split as a tag-part and the block size. Basically, the cache is split as many-byte blocks and tag each entry maps to a block and the index, or offset, is added to the address to address a byte.

So the binary addresses are 8-bits long. And based on the question the block seems to be 8 bytes long (hence 3 LSB bits for Index, also called offset). This leaves 5 additional bits for tag (Remember addresses are 8 bits long).


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