I was reading lecture notes of Universiti Malaysia Perlis when I am came across following question:

A computer consists of a CPU and an I/O device $D$ connected to main memory $M$ via a shared bus with a data bus width of one word $(16-bits)$. The CPU can execute a maximum of $10^6$ instructions per second. An average instruction requires $five $ processor cycles, $three$ of which use the memory bus. A memory read or write operation uses $one$ processor cycle. Suppose that the CPU is continuously executing “background” programs that require $95$% of its instruction execution rate but not any I/O instructions. Now very large blocks of data are to be transferred between $M $ and $D$.

Estimate the rate if DMA transfer is used.

P.S. Assume that one processor cycle equals one bus cycle.

The answer says:

$$10^6 * (0.05 * 5 + 0.95 * 2) = 2.15 * 10^6$$

Can someone explain the reasoning behind the answer ?

I could understand that $0.05$ is percent of time devoted by CPU and $0.95$ is the percent of time devoted by DMA, but what about $5$ and $2$ ? If it has something to do with cycles, then I did not understand the logic.


2 Answers 2


After reading more about it and reading the question again and again, I understood the logic

The question says that on an average an instruction requires $5$ $cycles$ and the CPU is busy $95$% of the time in executing those instructions. Out of these $5\ cycles$, $3\ cycles$ are needed for memory operations. During this time $DMA$ cannot access the memory.

So only $2\ cycles$ are left for $DMA$ to use for 95% of the time. For 95% time DMA uses $$0.95 * 2\ cycles$$

For rest 5% time, CPU isn't executing instructions, so all cycles are available, so DMA uses $$0.05 * 5\ cycles$$

Total cycles available for DMA $$(0.05 * 5 + 0.95 * 2)\ cycles$$

In $1 second$, CPU can execute $10^6$ instructions. So rate of transfer is

$$ 10^6 * (0.05 * 5 + 0.95 * 2) = 2.15 * 10^6 $$


we can see it like-wise also (I guess), i made it like a reasoning maths questions :P

In DMA , we don't need direct intervention of CPU , its DMAC which helps in controlling the data transfer.

let us take , CPU is fed with 100 instructions (replace those 10^6, as it says , cpu can execute - MIPS). For 100 instns it will require ~500 cycles . Now divide this into two sections so for 95 * 5 cycles , DMA will use 95 * 2 cycles (as during 3 cycles mem bus is busy ), and the remaining cycles 25 (=500-95 * 5) will be consumed by the IO device. now sum up (95 * 2)+(5instn * 5cycles)=2.15 (words per second) just multiply it with 10^6 for the case when 10^6 instn are fed.(2.15 * 10^6)


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