The question is not specific to any processor. Can I have an assembly instruction, like:
ADD R1 R0 R0
R1 is the destination.
My understanding is that, if the register file in a processor supports 2 simultaneous reads in a clock cycle (i.e. 2 read ports), two different registers can be read. But for 2 same input registers, this case has to be handled explicitly wherein the input can be duplicated after reading the first operand, and if that is not supported, the register file MUST have 2 read ports in one clock cycle, if not it might lead to a structural hazard.
I would like to know if my understanding is right.
And also do, any processors (current/old) handle this case, explicitly.
Thanks in advance.