The question is not specific to any processor. Can I have an assembly instruction, like:

 ADD R1 R0 R0

R1 is the destination.

My understanding is that, if the register file in a processor supports 2 simultaneous reads in a clock cycle (i.e. 2 read ports), two different registers can be read. But for 2 same input registers, this case has to be handled explicitly wherein the input can be duplicated after reading the first operand, and if that is not supported, the register file MUST have 2 read ports in one clock cycle, if not it might lead to a structural hazard.

I would like to know if my understanding is right.


And also do, any processors (current/old) handle this case, explicitly.

Thanks in advance.


R1 <- R0 + R0 works in every processor that permits three register operands. Nothing special needs to be done to deal with the same register driving multiple read ports.

Each register-file read port is just a multiplexer. If you have $N$ registers driving the $N$ inputs of one $N$-to-$1$ multiplexer and the same $N$ registers driving the $N$ inputs of a different $N$-to-$1$ multiplexer, there's no constraint that says that both multiplexer selects can't be set to the same register.

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    $\begingroup$ It might also be worth noting that for the original Pentium 4 add self-to-self would be preferred over left shift by 1 since the former would use the fast ALU. Such operations may also be detected in decode/rename as part of idiom recognition (e.g., some x86 implementations recognize subtract self and xor self as zeroing instructions). $\endgroup$ Jan 1 '15 at 16:58

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