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I have always wondered why is computer architecture in $2^n$ bits. We have 8 / 16 / 32 / 64-bit microprocessors or for that matter other parts of computer are also in power of 2 bits.

The only logic I could understand from my reasoning is that usually computer design process starts from lower amount of bits. For example : Say I want to design a Full adder to add 16 bit numbers. So I would first design a digital circuit to add 2 bits (one from number A and other form number B). Then I would replicate this circuit 16 times. So this will give me 16-bit full adder.

Is my reasoning correct ? Is there some other reason also ?

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  • $\begingroup$ Note that early computers didn't necessarily follow this convention. For example, EDSAC had 1024 memory locations, each holding 17 or 18 bits. UNIVACs had all kinds of word sizes (at least 18, 30, 36 bits). $\endgroup$
    – David Richerby
    Jan 4, 2015 at 16:46
  • $\begingroup$ Did you ever notice that balanced binary trees have a number of nodes at each level that is a power of 2. Strange coincidence! $\endgroup$
    – babou
    Jan 4, 2015 at 22:04
  • $\begingroup$ @DavidRicherby I Agree. But $2^n$ has become a general standard and I am curious to know why.. $\endgroup$
    – SimpleGuy
    Jan 5, 2015 at 1:01
  • $\begingroup$ @babou Is that intended as an oblique hint? If so, it's so oblique that I don't understand it. $\endgroup$
    – David Richerby
    Jan 5, 2015 at 8:31
  • $\begingroup$ @DavidRicherby It is more a search suggestion than a hint. I am not very happy with the answers. I was only noting that binary structure are used a lot, including in places where we could conceivably use non-binary structures (ternary or others). Trying to identify the reasons for the binary bias in other situation might give clues for this specific aspect of convergence of memory unit size on povers of two. One clear aspect is that bits are used optimally when addressing spaces that are a power of two. $\endgroup$
    – babou
    Jan 5, 2015 at 10:42

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Not necessarily, for instance, look at the memory bus width in modern day GPUs, they would have values of 192, 384, 768(while 128, 256.... are common).

One could argue that 192 is a sum of powers of 2 (2^7+2^6), sure, but what number isn't?

That being said, any memory modules directly associated with a microprocessor or a microcontroller will have capacities in powers of 2. Traditionally registers will be 8,16, 32 or 64 bits long (though 10-bit and other non conventional widths exist).

A processor (or controller) with an n-bit register can address upto 2^n addresses (i.e, 0-(2^n)-1 bytes). Hence without changing the processor, one can extend the memory associated with it although exceeding the addressing space beyond what the processor can manage will be redundant.

In many DSPs, the memory associated with the processor is in 2^n multiples as many of the signal processing algorithms can be made very efficient when calculating this way.

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    $\begingroup$ Perhaps the point of 192 is not that it's a sum of powers of two, or even a sum of two powers of two, but that it's the sum of two consecutive powers of two, i.e., half-way between two powers of two. (Not sure why that would be relevant to anything, though). The rest of your answer doesn't really address the question, though. Sure, with an $n$-bit register, you can address $2^n$ memory locations. But why is $n$ itself typically a power of two? $\endgroup$
    – David Richerby
    Jan 4, 2015 at 20:00
  • $\begingroup$ Note that, in some cases (not GPUs) the memory bus width is not a power of two because of EDC bits (error detection & correction. Sometimes just detection.). $\endgroup$
    – TEMLIB
    Jan 4, 2015 at 20:04
  • $\begingroup$ @DavidRicherby The Intel 4004 was a 4 bit processor, no reason for this number, it was what was possible at the time... Then later came 8-bit(8008..), 16-bit and so on. This had become the industry standard. So every other manufacturer was just following standards. Back in the day, Moore's law was applicable practically up until 7 or 8 years ago when some physical limitations of silicon had started to show. So, the number of logic modules they could fit doubled and that might explain the 2^n pattern. This trend stopped at 64 bit as it can already address an impractical amount of memory. $\endgroup$
    – d34df3tu5
    Jan 4, 2015 at 20:33
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    $\begingroup$ @d34df3tu5 .."This had become the industry standard" My Question is this only, Why has this become an industry standard, what convenience does it give the "industry". Is "easy of replication" (as I mentioned in question) the only reason ? $\endgroup$
    – SimpleGuy
    Jan 5, 2015 at 0:53
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    $\begingroup$ @d34df3tu5 Also my Question is not about "what other architecures exists other than $2^n$ bits" but it is about why $2^n$ is so popular. $\endgroup$
    – SimpleGuy
    Jan 5, 2015 at 0:55
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Some say that the IBM STRETCH (1961) introduced 8bits bytes :

http://en.wikipedia.org/wiki/IBM_7030_Stretch

Until the late 70s, computers used other sizes and multiples, for example 36bits = 8 characters of 6 bits. Early computers used only uppercase letters and numbers, using 6bits per character was more efficient.

Anyway, ask wikipedia : http://en.wikipedia.org/wiki/12-bit, http://en.wikipedia.org/wiki/18-bit...

There can be several explanations for the fact that all modern computers use 8bits bytes and multiples thereof. All monolithic microprocessors used that (8080, 6502...), 7 or 8bits ASCII was necessary for making text in uppercase and lowercase with internationalisation. Using powers of two all the way down must be appealing for computer designers...

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    $\begingroup$ ".. There can be several explanations for the fact that all modern computers use 8bits bytes and multiples thereof" What are those ? The question is about that only. $\endgroup$
    – SimpleGuy
    Jan 5, 2015 at 0:58
  • $\begingroup$ I though I gave some hints as why 8bits may be appealing. Explanations can be found by reading about old computers, but there is no simple answer. And adders can have any width, there is no benefit to have a power of two. IEEE double precision FPUs use 53 bits adders. $\endgroup$
    – TEMLIB
    Jan 5, 2015 at 21:10

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