I'm reading multi-level cache and came across a question through which i got confused. I've read that

  • Between processor and Cache Word/ Byte is transfered
  • Between Cache and Main memory Block(Block of words) is transfered.
  • If there is a miss in lower level cache and hit in higher level cache, first Block of words is transfered from higher level cache to lower level cache and then particular words is transferred to the ptocessor from lower level cache.

In case of multi-level caches cache at lower level generally has lower size as compared to cache at higher level. Hence Block size of lower level cache is generally smaller than block size of higher higher cache.

So, How actually Block of words is transferred between caches.

For instance suppose there two caches $L_1$ and $L_2$ with block size 4 words and 16 words respectively, connected with a databus having capacity to transfer 4 words at a time. Now Suppose there is a miss in $L_1$ cache and a hit in $L_2$ cache. Then Do we transfer 16 words or only 4 words from $L_2 \rightarrow L_1$

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  • $\begingroup$ I believe you are mistaken. The block size should be the same for all levels. $\endgroup$ – ultrajohn Jan 19 '15 at 16:11
  • $\begingroup$ @ultrajohn question that is asked has explicitly mentioned that both cache has different block size $\endgroup$ – Atinesh Jan 19 '15 at 17:29
  • $\begingroup$ To reduce the miss penalty on L1 or to reduce the hit time of L2, the "natural" answer would be 4 words. The amount of words to be transferred between L1 and L2 is also dependent on the amount of associativity in the L1 cache. If L1 is 2-way set associative, then by definition you would have to transfer 8 words of data from L2 to L1. However, this would make the miss penalty of L1 longer, a situation that you will never want. $\endgroup$ – ultrajohn Jan 20 '15 at 2:36

It depends. What is the level of associativity of L1? If it's a direct mapped cache, then naturally, you will have to transfer 4 words of data from L2 to L1. If it's a 2-way set associative, then 8 words. This makes the interface between L1 and L2 as simple as possible given their configurations.

The idea is to make the hit time of L1 and miss rate of L2 as low as possible.

  • $\begingroup$ For instance lets suppose both cache are direct mapped. As we can see L2 Cache has Block size 16 words. So it manages the whole block at a time. If in case of miss in L1 the whole block of 16 words containing the word should be transferred from L2 to L1. $\endgroup$ – Atinesh Jan 20 '15 at 4:50
  • $\begingroup$ I think that's possible but it would make the interface between L2 and L1 complicated. $\endgroup$ – ultrajohn Jan 20 '15 at 7:27

Block sizes (aka Cache line lenghts) can be different on different levels of caches. L1 caches should be optimised for the type of access the CPU does while L3 caches should be optimised for the burst lenght and data width of the attached DRAM memory.

It is possible to fill/spill only one block of the L1 with a larger block sized L2 (in your example 4 words). On write back, either the whole L2 block is marked as modified, or use sub-blocking (effectively reducing block size without raising associativity).

One advantage with using the same size is probably with exclusive caches (AMD did that many times) : As soon as a block is in L1, copied from L2, the L2 block can be made available for new data.


Many examples there : http://www.7-cpu.com/ Using different block sizes across different cache levels seems very rare : Several recent x86 use 64Bytes, ARMs 32Bytes, PowerPCs 128Bytes, but they keep the same size on all levels. Note also the bus width : Internal busses can be extremely large, able to transfer 16 or 32 bytes in one cycle.


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