I am not sure I understand the question.
When designing a CPU, you decide how many pipeline stages it will have and accordingly how much work is done at each stage.
Often, all the parts of the CPU work at the same frequency (well, this is not really true, but...), so the most complex part will be what limits the frequency that the CPU will be able to achieve.
Some CPUs are optimised for high frequency and have many pipeline levels (ex : Intel Pentium IV, AMD Steamroller). Good for number crunchers.
Some CPUs are optimised for lower frequencies but cram more work for each pipeline level (ex. : Intel Core, Apple A8...). This option is often more power efficient.
Deeply pipelined CPUs waste more cycles than narrow ones when the pipeline must be emptied : mispredicted branch, interrupt... The number of cycles wasted is higher, but as the frequency should also be higher, the delay for each cycle should be a bit shorter than for a short-pipelined CPU.
[Maybe you should give more context to your question. This answer was probably not what you were looking for ;-)]