Useful computing devices require feedback, which makes it possible to have one circuit element perform an essentially-unlimited number of sequential computations. Usable feedback circuits must contain sections whose total number of inputs (counting both the ones that are fed back from outputs and those that aren't) exceeds the number of outputs which are fed back to input (the only way the number of inputs wouldn't exceed the number of fed-back outputs would be if the circuits didn't respond in any way to outside stimuli). Since perfectly reversible-logic functions can't have more inputs than outputs, it's not possible to construct from them any of the feedback structures required to perform any non-trivial computing tasks repeatedly. Note that with the CMOS technology used in today's computers, feedback is required to ensure that results reported by computations in different parts of a circuit are made available simultaneously to other parts, since if they weren't the relative timing with which the signals arrive would constitute "information" which could not be perfectly passed downstream; other technologies might make it possible to have many gates propagate signals at precisely the same rate while retaining reversibility, but I know of no practical technology for that.
Note that from a CS perspective, it's trivial to make a computing process reversible if one has initially-empty storage medium whose size is essentially proportional to the number of steps times the amount of state that could change in each step. This claim does not contradict the claim of the previous paragraph, since storage proportional to the number of steps will require circuitry proportional to the number of steps, which will imply circuitry proportional to the amount that would be required if all feedback were eliminated.
If one is allowed to have outputs which are ignored if, given proper input conditions, they will never go high, then it might be possible to design a system that would, in theory, benefit from reversible logic. For example, if one had an algorithm that operated on a 256-word chunk of RAM and one wanted to use a "reversible-logic CPU" that performed 1,000,000 operations per second and each operation updated either a register, the program counter, or one word of RAM, one could use a "reversible CPU" which would:
- ran a bunch of instructions and, on each, send whatever was overwritten to a LIFO buffer
- after a bunch of instructions had executed, copy the RAM into an initially-blank "forwarding" buffer
- using the values in the LIFO, run all the computations in reverse
- overwrite the contents of the main RAM with the forwarding buffer, which would be erased in the process.
The above recipe could be repeated any number of times to run the algorithm for an arbitrary number of steps; only the last step of the recipe wouldn't be reversible. The amount of energy spent per algorithmic step in non-reversible operations would be inversely proportional to the size of the LIFO, and thus could be made arbitrarily small if one were building to build a large enough LIFO.
In order for that ability to translate into any sort of energy savings, however, it would be necessary to have a LIFO which would store energy when information was put in, and usefully return that energy when it was read out. Further, the LIFO would have to be large enough to hold the state data for enough steps that the any energy cost of using it was less than the amount of energy it usefully saved. Given that the amount of energy lost in the storage and retrieval of N bytes from any practical FIFO is unlikely to be O(1), it's unclear that increasing N will meaningfully reduce energy consumption.