From Tanenbaum's Structured Computer Organization:
Figure 2-4(a) illustrates a pipeline with five units, also called stages.
If one pipeline is good, then surely two pipelines are better. One possible design for a dual pipeline CPU, based on Fig. 2-4, is shown in Fig. 2-5. Here a single instruction fetch unit fetches pairs of instructions together and puts each one into its own pipeline, complete with its own ALU for parallel operation.
A different approach is used on high-end CPUs. The basic idea is to have just a single pipeline but give it multiple functional units, as shown in Fig. 2-6. The definition of ‘‘superscalar’’ has evolved somewhat over time. It is now used to describe processors that issue multiple instructions—often four or six—in a single clock cycle. Of course, a superscalar CPU must have multiple functional units to hand all these instructions to. Since superscalar processors generally have one pipeline, they tend to look like Fig. 2-6.
I wonder what counts as a pipeline?
In Figure 2-4(a), a pipeline consists of 5 stages.
In figure 2-5, two pipelines share the same instruction fetch unit, but why isn't it a single pipeline?
In figure 2-6, a pipeline has multiple functional units, but why isn't it multiple pipelines?