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say that you have a 128 bit (32*4) VLIW word. Can each 32 bit sub-word contain any operation (ADD,CALL,BRANCH,...) if there are no hazards or can each sub-word only specify one functional unit (so if the BRANCH functional unit doesn't get used, that sub-word becomes a NOP)?

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Usually, VLIW instruction sets dedicate bit fields to functional units (not necessary multiples of bytes, or the same width for all units), and when some parts are unused, they are configured as NOPs.

Of course, there are exceptions, sometimes execution units are coupled, or special configurations are provided for long immediates... There is no absolute rule.

You should look at sample implementations, like the 48bits SHARC DSPs, or the ST200 family.

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As TEMLIB's answer indicates, VLIWs generally limit what operations can be encoded into each slot of the instruction word.

The primary constraint is actually structural hazards. The area and power cost of allowing all operations to be multiplications or all operations to be memory accesses would be excessive for most workloads.

VLIW encoding has two prominent goals. The primary goal is to express operation independence, the absence of data (and structural) hazards within an instruction word; hardware does not have to check for these hazards within an instruction word. A secondary goal is to minimize instruction routing complexity. Classic VLIW design where a single instruction word size is supported and nops are placed in unused slots provides the simplest routing of operations, a fixed mapping (as well as simple instruction fetch).

[fetch width, operation count variability/immediates, buffering, using free space in previous instruction word as addendum for next instruction word, problem with multiple fetch cycles for single issue cycle [immediates do not have to be decoded, so could be placed in next fetch chunk, a skewed pipeline could allow operations in a single execution word to be fetched later; these steal space from the next fetch chunk/VLIW]

The additional cost of supporting less expensive operations along with an expensive operation can justify bundling such into a single issue port, but given support for wider execution the benefit of such flexibility is reduced. Such is also nearly indistinguishable from a wider virtual instruction word with eliding of nops with a minimum number of nops elided.

(Superscalar processors have similar issue constraints.)

Since the placement of operations within an instruction word does not imply execution ordering — all operations in a VLIW are independent (exceptions include first-taken branch escapes where multiple branches can be in a single instruction word and only the first taken branch is effective)—, flexibility in placement is typically less useful.

Fixed format instruction words not only provide simpler operation routing but also allow the size of the operation slot to match the requirements for encoding the operations available in that slot. This can improve code density. Decoding logic is also simplified by each slot's decoder only needing to support the operations and encodings allowed by that slot. Such simplifications not only reduce power and area but can also modestly reduce critical path delay which can translate into a faster clock or shallower pipeline.

It is also not uncommon for an operation slot to use encoding space from another slot to increase the size of the operation. This is primarly used to extend immediate values, using the entire operation slot, but conceptually using only part of the other slot's encoding space or using the space to encode register identifiers or opcode extensions would be possible.

Having a fixed maximum instruction word length equal to the fetch width is typical. If an instruction word crossed a fetch boundary, either the front end would have to handle stalling the pipeline when an instruction word is fetched over two cycles (modestly increasing hardware complexity) or software would have to guarantee that enough of the instruction word is buffered from the previous fetch that the next fetch chunk would complete the instruction word (restricting control flow targets, include exception return points).

(You might notice a similarity to SIMD with respect to simplification of routing: SIMD simplifies routing of operands to functional units by using a long data word.)

Encoding Examples

Sun Microsystem's MAJC family of architectures may come closest to allowing every slot to provide any operation. The encoding used 32-bit operation slots with the first two bits of the first operation slot encoding how many operations were in the instruction word (between one and four). The first slot was the only one that could perform control flow and memory access operations and because of these extra operations and the loss of two bits to encode the instruction word length the first slot could not perform all compute operations. The other three slots were uniform in their support of compute operations; this was intended to simplify design by allowing simple copy-and-paste of these functional units. (One branch or memory operation per four operations seems imbalanced for more general purpose workloads, but such might be acceptable for compute-intensive workloads. MAJC ended up targeting graphics and multimedia applications.)

STMicroelectronics' ST240 ("ST240 core and instruction set Reference Manual" (PDF)) provided a "stop bit" with each 32-bit operation slot ("syllable") to indicate the end of a variable-length instruction word. Like MAJC, this helps avoid the use of padding nops; unlike MAJC, this mechanism is not constrained to a maximum instruction word length. In addition to the implementation-independent encoding constraints such as no data hazards, implementation-dependent constraints allowed control flow operations only in the first slot, multiplications only in odd word (not syllable) addresses, immediate extensions and a few specific operations only in even word addresses, only one operation per instruction word ("bundle") using the load-store unit, and a few other restrictions. Restricting control flow operations to the first slot facilitates quick detection and action on such operations; other restricts primarily simplify operation routing and avoiding structural hazards.

Tilera TILE-Gx used a fixed 64-bit instruction word, but used two bits to indicate if the word used two-operation X format (if both bits are zero) or three-operation Y format. The Y format provided two 24-bit operation encodings (Y0 and Y1) and one 14-bit encoding (Y2) that also used the three states from the two format-specifying bits to indicate a "mode" for the operation. The X format provided two 31-bit operation encodings. The Y2 slot could execute loads and stores; the Y1 slot could execute arithmetic, logical, and jump register operations; and the Y0 slot could execute multiply, arithmetic, and logical operations. The X1 slot combined the capabilities of the Y2 and Y1 slots and the X0 slot had the capabilities of the Y0 slot. Aside from the potential combining of slot capabilities and slight variability in slot size, this is effectively a classic VLIW encoding.

The Philips TriMedia TM3270 ("The TM3270 Media-processor", Jan-Willem van de Waerdt (PDF)) had five slots per instruction word and used a 10-bit template field to encode the size of each slot for the next instruction word. (Jump target instruction words are always uncompressed, avoiding the problem with multiple next instruction words following branches and register-based jumps.) A slot could be between 0 (nop) and 42 bits long. All slots could have simple ALU operations and immediates. Slot 1 could DSP ALU operations, and FP ALU operations; slot 2: jumps, multiplies, FP cmp, and hard FP; slot 3: DSP ALU, multiply, and FP cmp; slot 4: jumps, DSP ALU, FP ALU, and store; slot 5: load, store, and special operations using the load-store unit. In addition, slots could be merged to have more sources and destinations: merging slots 1 and 2 or slots 3 and 4 provides one set of operations, merging slots 2 and 3 provided another set, and merging slots 4 and 5 provided a third set of operations.

Fujitsu's FR500 ("FR500 VLIW-architecture High-performance Embedded Microprocessor", Takao Sukemura (PDF)) is interesting in have six potential issue slots but only supporting up to four operations per instruction word. The potential issue slots are: integer-0, float/media-0, integer-1, float/media-1, branch-0, and branch-1. Like the ST240, the FR500 uses a bit per 32-bit operation slot to indicate the end of the instruction word. If a potential issue slot is unused, the next slot is shifted into its place.

The Cydrome Cydra-5 ("The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-Offs" (PDF) was an early VLIW which used a fixed-length 256-bit "instruction container". This could hold either six 40-bit serial operations ("UniOps") or a seven operation MultiOp with different-sized slots: 39-bit FADD/ALU, 39-bit FMPY, 44-bit Mem1, 28-bit Mem2, 33-bit AADD1, 32-bit AADD2/AMPY, and 41-bit Branch.

(Other examples of VLIW encodings include the Multiflow TRACE, the Texas Instruments TMS320 C6xxx, and Intel Itanium.)

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