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Can we distinguish instruction level parallelism and SIMD instructions (SSE, 3D now...) ?

Or is SIMD instructions one of the multiple ILP techniques ?

Thank you.

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  • $\begingroup$ Are you asking, whether SIMD instructions are just "complex-instructions" / "hardcoded-mini-functions" inside CPU, which use ILP? $\endgroup$
    – kravemir
    Commented Apr 23, 2015 at 9:50
  • $\begingroup$ SIMD is often referred to as data level parallelism. Parallelism within an instruction is generally not considered ILP, even if implemented in a manner that executes operations in parallel using multiple functional units. ILP is architecture- and compiler-dependent; complex instructions reduce ILP at the same performance.. $\endgroup$
    – user4577
    Commented Apr 23, 2015 at 10:39
  • $\begingroup$ @Miro In fact I don't know what I am asking exactly. I just noticed that reading Wikipedia about these subjects was not sufficient to understand the relations betweens techniques/technologies... $\endgroup$
    – user7060
    Commented Apr 24, 2015 at 7:39
  • $\begingroup$ @PaulA.Clayton Thanks. Are most of the SSE3 instructions implemented in a manner that execute operations in parallel using multiple functional units ? $\endgroup$
    – user7060
    Commented Apr 24, 2015 at 7:45
  • $\begingroup$ @user7060 Well, that type of questions usually gets closed as "unclear what are you asking". And even you don't know what are you asking,.. ehm... $\endgroup$
    – kravemir
    Commented Apr 24, 2015 at 7:51

2 Answers 2

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Instruction-level parallelism, data-level parallelism, loop-level parallelism, and task-level parallelism are not well defined terms. The definable concept is parallelism. Two operations can run simultaneously (or "in parallel") when the portions of the state they write are non-overlapping, and when the portion of the state written by each operation does not overlap with any of the state read by the other operation.

So two different instructions can run in parallel when the registers and memory they read and write don't overlap. The sub-operations of a SIMD instruction can run in parallel because they are defined to only perform sub-operations that each read or write different portions of a vector register or cache line.

I like to say

parallelism is as parallelism does

and what parallelism does is run multiple operations simultaneously.

The benefit of SIMD instructions, over just using 4 or 8 or N individual instructions that perform the same sub-operations, is that the fetch, decode, renaming, and scheduling units of the processor don't need to do as much work to exploit the parallelism between the sub-operations.

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  • $\begingroup$ Pipelining adds another wrinkle in that multiple instructions are being handled at the same time but going deeper rather than wider in a certain sense does not process instructions in parallel. Yet doubling pipeline depth is "equivalent" to doubling pipeline width. $\endgroup$
    – user4577
    Commented Apr 24, 2015 at 11:24
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I would characterize ILP as a stream of instructions going into the CPU and the instructions execute partially overlapped but in a normal serial order (assuming there is nothing but ILP going on).

SIMD is totally different. It's more like just having instructions with really really large registers, like 1024 bits wide, where the instructions operate on the register cut into pieces. For a 1024 bit add that cuts into 32-bit chunks, you can think of a 1024-bit adder that simply doesn't do a carry across boundaries between the 32-bit chunks in the register.

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