LW R2, 0(R1) CMP R3, R2 CMP R7, R5
the LW instruction stalls the first CMP so the second one will execute first. Wouldn't this cause the flags register to contain the wrong value since it expects the second CMP to be the last one that updates the flags register?
I'm not sure about this one: does an ADD instruction ALWAYS update the overflow flag (1 if overflow and 0 if no overflow).
LW R2, 0(R1) ADD R4, R3, R2 ADD R7, R5, R6
Same thing here: will the overflow flag be wrong if the first ADD wouldn't overflow but the second one will. The second ADD executes firsts and sets the overflow flag. After that the first ADD executes, doesn't overflow and sets the overflow flag to 0?