LW R2, 0(R1)
CMP R3, R2
CMP R7, R5

the LW instruction stalls the first CMP so the second one will execute first. Wouldn't this cause the flags register to contain the wrong value since it expects the second CMP to be the last one that updates the flags register?

I'm not sure about this one: does an ADD instruction ALWAYS update the overflow flag (1 if overflow and 0 if no overflow).

LW R2, 0(R1)
ADD R4, R3, R2
ADD R7, R5, R6

Same thing here: will the overflow flag be wrong if the first ADD wouldn't overflow but the second one will. The second ADD executes firsts and sets the overflow flag. After that the first ADD executes, doesn't overflow and sets the overflow flag to 0?


The flags register is handled using one of the standard techniques for dealing with dependencies in out-of-order processors. Either

  1. the registers are renamed (there are multiple physical flags registers, and the renaming and retirement mechanisms make sure the correct physical flags register is being used by each instruction) or

  2. the scheduler respects anti- and output- dependencies, in which case the two CMP instructions execute in-order because the second is output-dependent on the first.

Same thing with ADD instructions. In a machine with ADDs that set an overflow flag, the overflow flag needs to be handled either by renaming or by stalling on anti- and output- dependencies.

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  • $\begingroup$ This is correct. I had an email exchange with an Intel compiler engineer and he said that modern processors rename the flag register at the bit level. $\endgroup$ – Olsonist May 29 at 18:36

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