Computer Architecture, cache hit and misses

I am currently enrolled in a computer organization and design class, which I am struggling mightily with, and I have a final homework in my class that I need to get a perfect score on. One of the questions covers cache hit-misses, and the lecture we had on the subject was relatively brief. The question I have having issues with is:

A processor has a CPI of 1.4 with level 1 caches with a 100% hit rate. When running benchmarks, the level 1 instruction cache has a 1% miss rate and the level 1 data cache has a 3% miss rate. 30% of the instructions access memory through load and store operations. Main memory has a 50 nano second access time and the clock is running at 2.5 GHz.

What is the actual CPI of the processor with just the level 1 caches?

A level 2 cache is added to the processor. The hit time of this cache is 1.5 nanoseconds, and it has a global miss rate of 0.5%. Compute the actual CPI of the processor after the addition of the level 2 cache.

What is the speedup achieved by adding the level 2 cache?

So my first attempt is this:

I-cache miss rate = 1%
D-cache miss rate = 3%
Miss penalty to main memory = main memory access time / clock time
50 ns / .4 ns per clock cycle = 125 clock cycles
Base CPI = 1.4
Load and store = 30% of instructions
Main memory access time = 50 ns
Processor clock = 2.5 GHz

What is the actual CPI of the processor with just the level 1 caches?

Instruction miss cycles = I x 1% x 125 = 1.25 x I
Data miss cycles = I x 30% x 3% x 125 = 1.125 x I
Total number of memory-stall cycles is 2.375 I
Total CPI including memory stalls is 1.4 + 2.375 = 3.775

A level 2 cache is added to the processor. The hit time of this cache is 1.5 ns and it has a global miss rate of 0.5%. Compute the actual CPI of the processor after the addition of the level 2 cache.

Secondary cache access time = 1.5ns
Processor clock = 2.5 GHz
Miss penalty for an access to second-level cache = 1.5ns / .4 ns per clock cycle = 3.75 clock cycles
For a two level cache, total CPI is the sum of the stall cycles from both levels of cache and the base CPI
1.4 + (.005 x 125) + (.005 x .3 x 125) + (.01 x 3.75) + (.01 x .3 x 3.75) = 2.26125
*****This is where I'm most unsure. The "global miss rate of 0.5%" is throwing me off, and I'm not sure I performed this calculation correctly.**

What is the speedup achieved by adding the level 2 cache?
3.775 / 2.26125 = 1.67
***This answer is dependent on the result from the calculation above. If I did that wrong, this answer will be different.

• It'd be helpful if you wrote what holds you back form answering this question. What have you tried? Where did you get stuck? We do not want to just do your (home-)work for you; we want you to gain understanding. However, as it is we do not know what your underlying problem is, so we can not begin to help. See here for a relevant discussion. If you are uncertain how to improve your question, why not ask around in Computer Science Chat? May 6, 2015 at 22:37
• I completely understand, let me out line what I've tried. May 7, 2015 at 2:29
• Sorry, I've added what my first attempt was. My apologies for not outlining it earlier. May 7, 2015 at 2:38

You may wish to ask your TA/Prof. what they mean by "0.5% global miss rate". The way I read it is the following:

Out of $x$ accesses to the L2 cache, $0.005x$ accesses are a miss.

This interpretation makes more sense than assuming the miss rate is out of all the store/load instruction.

So each miss of the L1 cache becomes an access to the L2 cache, and out of these, 0.5% are a miss at the L2 cache. From here, it seems you can fill out the details by yourself, building on your own attempts.