The Problem: A CPU produces the following sequence of read addresses in hex. Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address produces a hit or miss for fully associative cache
20 0010 0000
04 0000 0100
28 0010 1000
4C 0100 1100
Here is the format that we use for the address
I am not quite sure what the addr field is for but I am assuming its the actual address in RAM.(Please correct me if this is wrong)
I know that it can't be apart of the TAG because the TAG portion is made up of bits and C in one of the example addresses above is not a bit(it's a hex digit)
Here is the table I made thus far to store my results.
The red entry I highlighted was the entry I am not sure about. I know that with 3 index bits, the cache will have 8 cache lines. When the CPU goes to the cache for the third address, will it be a hit because the tag already exists(1st cache line) and not add that data or will be a miss and the data will be added because the cache isn't full yet?