# Is a 2 address machine more likely to follow a RISC or CISC design?

To solve this problem I first looked up the different terms.

• RISC is a microprocessor architecture that has smaller/simpler set of instructions
• CISC is a microprocessor architecture that has larger/more complex set of instructions
• 3, 2, 1 address machines just mean how many addresses are in an instruction

When first investigating the relationship between RISC vs CISC and n-address machines, with the help of the slide below, I was able to quickly associate 3 address with CISC and 0 address with RISC.

I saw that 3 address instructions were much more complicated than 0 address and therefore would make sense for CISC design. Similar reasoning for 0 address machine and RISC design. How would you make the distinguish for CISC and RISC with the address sizes in the middle - 1 and 2?

The problem is that the terms RISC and CISC are marketing terms, not science or engineering terms. The terms are supposedly acronyms for "Reduced Instruction Set Computing" and "Complex Instruction Set Computing." Your assumption that 3 addresses is much more complicated than 0 addresses is logical, but there is no logic here, and typically 3-address instructions are associated with RISC and 2-address instructions are associated with CISC (and 1-address and 0-address instructions aren't very common any more, so aren't associated with either RISC or CISC).

The term RISC is generally associated with instruction sets that have the following characteristics:

1. Fixed width instructions. Usually 32-bits or 16-bits. This makes it easier for the instruction decoder to find the boundaries between instructions. In CISC machines, by contrast, the different instructions can range in length from 8-bits to as much 64-bits. This makes the job of the instruction decoder somewhat harder in CISC machines, but can result in programs consuming less memory.

2. Fewer operand addressing modes. In a RISC machine typically each operator (add, sub, jmp, load) has only one available addressing mode for its operands (the a, b, c, d, and e in your picture.) Typically for arithmetic type instructions (add, sub, xor, ...) the only available addressing mode is register direct. The source operands are found in registers, and the result of the computation can only be placed in a register. Load and store type instructions typically have one operand that is register direct and the other operand is register indirect plus offset. Jump and branch type instructions will typically have a target operand that is pc relative. There will typically also be a few jump and branch type instructions with a register indirect target, and sometimes a jump instruction with an absolute target operand. The smaller number of operand addressing modes is typically the only way in which "RISC" instruction sets are actually reduced (compared to "CISC" instruction sets). The reasoning, again, has to do with trying to keep the instruction decoder as simple as possible in RISC machines. The simple operand addressing modes are easier to implement in a simple pipeline, and so the decoder in modern CISC machines often has to do extra work to crack instructions with complex operand modes into sequences of micro-operations that are more like RISC instructions.

3. There is a tendency for RISC architectures to have more register names available. Many RISC architectures have 32 registers, while many CISC architectures have only 8 or 16. This again has to do with making it somewhat simpler to exploit instruction-level parallelism with a simple pipeline. Having more available register names makes it possible for the compiler to use different register names for unrelated computations, without requiring the hardware to do register renaming.

4. RISC architectures tend to have "3-address" instructions, while CISC architectures tend to have mostly "2-address" instructions. The notion of "3-address" vs. "2-address" is also somewhat fuzzy (and somewhat mis-named). Every add instruction has 3 operands, 2 source operands and 1 destination operand. The real distinction is whether those operands are explicit or implicit. In a so-called "3-address" instruction you make all 3 operands explicit. In a so-called "2-address" instruction you make the destination operand explicit and one of the source operands explicit. The third source operand is implicit: it is always the same address as the destination operand. In a so-called "1-address" instruction only one of the source operands is explicit. The other source operand is implicitly either an accumulator register or the top of the stack, as is the destination operand. Finally in a "0-address" instruction all the operands are implicit (usually the two source operands are the top two values on the stack and the destination goes back on the top of the stack.)

To sum up: these are all marketing terms, and don't really mean much. The important concepts have to do with the relationship between different instruction-set design choices and how those choices make it easier or harder to implement hardware pipelines.

To understand the technical aspects which survive (as @WanderingLogic said marketting aspect dominated quite quickly), of the RISC/CISC dichotomy you need to consider four points:

• it is not really a dichotomy but more a continuum

• history is important: RISC came as a reaction to tentative to close the so called semantic gap. Don't look at how simple arithmetic is done, that will give you about no information, look for instructions like polynomial evaluation or function entry with automatic display setting and register savings. Those are the complex instructions which are absent in RISC and present in CISC. They introduced complications in the processor and their function could often be implemented more rapidly with a sequence simpler instructions, especially when not needed in their full generality. RISC is somewhat the result of a quantitative approach(1) to ISA design, trying to make the cost of the inclusion of an instruction justified by its benefit and its frequency of execution.

• history is important: RISC became popular at a time when implementing a 32-bit RISC on a single chip was just possible while for implementing a 32-bit CISC you either had to use several chips or space saving techniques which had an impact on performance. You can nearly define RISC as the answer to the question "how to get an high performance 32-bit CPU on that area?" When the space available on a chip increased, the RISC cpus became more CISCy.

Now, how to get an high performance 32-bit CPU on a small area?

• You can't rely on having cache on chip, so lot of registers to benefit from the locality of data access. Thus not an accumulator nor stack architecture. (Aspect carried over with the register windowing).

• Pipelining. That means overlappable instructions, thus again 2 or 3 operands or you'll have trouble to have independent instructions.

• Simplify decoding. Fixed width instruction. Thus wide enough to have 3 operands and as the cost of implementing 3 operands is mostly instruction width, you get that most RISC are 3 operands ISA.

Delayed jump is more or less the result of pipelining with decoding simplified to the extreme.

1) See Hennessy and Patterson.