0
$\begingroup$

The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 64 byte lines, how many bits are in each of the following address fields for the cache? 1) byte 2) Index 3) Tag?

I know that an address for specifying data within a cache is 64 bits.
I know that an address for a cache has to have the byte, index, and tag field so
byte + index + tag = 64
The index field should take up 13 bits to account for the 8192 byte lines

How many bits would be in the byte field though? I know that a processor processes one word at a time and each word consists of 8 bytes. A 64 byte cache line would contain 8 words. Would this byte field need to identify each word or each byte itself. If it was byte itself, it be 6 bits but if it was word it be 3 bits.

If I had to take a stab, I would say the byte field needs to be 3 bits to identify each word because it doesn't make sense for the processor to just process one byte. Can anyone confirm my suspicisions?

$\endgroup$
  • $\begingroup$ You should write down address bits : 64bits addresses =A[63:0]. 64bits bus = 8 bytes =A[2:0] for selecting bytes within a longword. 64bytes lines =A[5:0], 8192 lines = A[18:6], Tags = A[63:19] ... There is one tag per cache line, so 8192*25 bits for tags, 8129*64*8 bits for data. There is a few other details needed, for example one additional "Valid" bit per tag. $\endgroup$ – TEMLIB Jun 6 '15 at 18:43
  • $\begingroup$ So it would be 3 bits to select a word in a cache line? So I was correct? $\endgroup$ – committedandroider Jun 6 '15 at 18:54
  • $\begingroup$ Yes. 3 bits are needed (A[5:3]) for selecting which 64bits word is addressed within the 64 bytes cache line. $\endgroup$ – TEMLIB Jun 7 '15 at 11:41
  • $\begingroup$ Maybe this thread would help: cs.stackexchange.com/questions/33818/… $\endgroup$ – Ran G. Aug 21 '15 at 2:56
1
$\begingroup$

In a processor architecture of 64 bits the smallest single 'word' is 64 bits. that is each cyclic transfer from buffer to buffer occurs on a 64 bit buss. to identify a single byte of this native word in fact would only take 3 bits, but the actual register might in fact be 8-16 bits... if it was designed that way. the compiler that was designed to handle this would take all this into account and when you incremented a pointer it would do the conversion for you. as well as if the 'byte ' was actually an Unicode 16 bit character'. you need to look at the cpu programmers guide or manual for actual specifics and also the compilers manual, specifically with regards to data types and to addressing them.

$\endgroup$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.