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Let's consider the following MIPS (using pipelined arch.) assembly code:

lw r1,0(r2)
sub r4, r1, r6
and r6, r1, r7
or r8, r1, r9

the r1 value used in the second and third instruction will not be ready to use until the end of the 4th cycle of the pipeline, while the 2nd and the 3rd instruction need it at the 4th and 5th cycle respectively, i think for the 3rd instruction the problem can be resolved using bypass but for the 2nd instruction i am not sure ?? can anyone tell me how to avoid the RAW data hazard in this case ??

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It depends on the context. From a computer architecture perspective, you can insert a hazard detection unit that inserts a bubble in the pipeline when it detects this condition. It's shown top/left-ish in this picture from Patterson&Hennessy:

MIPS with hazard detection unit

The logic doesn't do anything unexpected, it detects the case that an instruction in the ID wants to read a register that a memory read in the EX stage will write to, the instruction from the ID stage is then killed and PC is "held" so the instruction will re-execute.

From a programmer perspective, suppose there is no hazard detection unit, just insert the NOP yourself.

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