Let's consider the following MIPS (using pipelined arch.) assembly code:
lw r1,0(r2) sub r4, r1, r6 and r6, r1, r7 or r8, r1, r9
the r1 value used in the second and third instruction will not be ready to use until the end of the 4th cycle of the pipeline, while the 2nd and the 3rd instruction need it at the 4th and 5th cycle respectively, i think for the 3rd instruction the problem can be resolved using bypass but for the 2nd instruction i am not sure ?? can anyone tell me how to avoid the RAW data hazard in this case ??