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According to the concepts of Pipelining,

In a single cycle different stages of different instructions are executed.

Now I have a bit of confusion here, that if a single processing element is there and can perform one processing at a time , then -

Do the preemption occurs multiple times in a single cycle in order to complete the different stages of different instructions inside the pipeline ?

If so, then does this mean that clock cycle duration is larger than the time quanta assigned to execute each stage of an instruction ?

For Example -

In Cycle 2 - below given stages of different instructions is to be executed -

IF of instruction5, ID of instruction4, EX of instruction3, MEM of instruction2,

WB of instruction1

OR the pipelining works only when there are multiple processing elements ? If I am missing something ?

Please explain or provide some helpful links for me to clear my doubts.

Thanks in Advance !

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    $\begingroup$ I'm having a bit of trouble understanding your question. In the classic DLX-ish RISC pipeline, there is one processing element, so pipelining works just fine with one processing element. Can you explain specifically what problem you think preemption would cause? $\endgroup$ – Pseudonym Jun 22 '15 at 6:17
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    $\begingroup$ In the classic RISC pipeline, yes and yes. Obviously it's possible to do superscalar/multicore/hyperthreaded RISC pipelines, but I assume we're not talking about that advanced stuff. $\endgroup$ – Pseudonym Jun 22 '15 at 6:53
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    $\begingroup$ Welcome to SE Computer Science. When asking a question you should give more details on what kind of documents you have been using to get more informattion on your subject, so as to tell us what you tried to understand and that we have some context to start with to understand what is blocking you. In this case, you are apparenlty quoting some document, but you do not say which. $\endgroup$ – babou Jun 22 '15 at 8:14
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    $\begingroup$ @Pseudonym i think i got it now - there are different circuits(execution subunits) within processor (classic RISC). I missed this while reading wiki and other sources over net. Thanks! $\endgroup$ – Bruce_Wayne Jun 22 '15 at 10:06
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    $\begingroup$ As I tried to point out in my welcome message, it is important to do the research work, especially on the net, before asking, and then ask only about aspects you still do not understand. In particular, you may search other SE questions, and the system automatically helps you for that. $\endgroup$ – babou Jun 22 '15 at 13:25
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Your question reminds me of an old joke:

If the Atlantic can be crossed in 7 days with one boat, you can cross it in one day, if you have seven boats available. (there are actually many variants)

Your problem is the problem of assembly lines in general, and that is the technical model of a pipelined processor.

On the assembly line for making car (I am of course simplifying), you will have one fellow placing the doors, another one placing the bumpers, one placing the wheels, another painting the car. They all work at the same time, doing their job in the duration of a single car making cycle, fixed by the big clock on the factory wall.

Every cycle, the last worker of the line finishes one car, while the first does the initial steps of making a new one. So there is exactly one car produced for each cycle. There is a single assmbly line (read: a single processor), producing one car with each cycle.

But it does not mean that it takes only one cycle to produce a car. It takes as many as there are stages in the assembly line. The rate of production (read processing rate) of one car per cycle is only a average over time.

The idea that that it is more efficient to have specialized workers working independently. But you do not want to keep them idle, when it is not their turn on a given car.

And, it may not be necessary that each car is built identically to the previous one. All you need is that each worker gets his part of the instruction(s), such as the diameter of the wheels to be placed, or the color of the paint. So the instructions may change, while going through the same assembly line to produce cars.

No one ever preempts the line to get something done. But all contributing workers are synchronized.

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