According to the concepts of Pipelining,
In a single cycle different stages of different instructions are executed.
Now I have a bit of confusion here, that if a single processing element is there and can perform one processing at a time , then -
Do the preemption occurs multiple times in a single cycle in order to complete the different stages of different instructions inside the pipeline ?
If so, then does this mean that clock cycle duration is larger than the time quanta assigned to execute each stage of an instruction ?
For Example -
In Cycle 2 - below given stages of different instructions is to be executed -
IF of instruction5, ID of instruction4, EX of instruction3, MEM of instruction2,
WB of instruction1
OR the pipelining works only when there are multiple processing elements ? If I am missing something ?
Please explain or provide some helpful links for me to clear my doubts.
Thanks in Advance !