Assume the CPU has 64 data lines. Then Z reading cycles will be needed to load an array of 12 double-precision floating-point numbers, each number coded in eight bytes, from the main memory into the CPU. Z = ?

So I'm looking at some of the past exam questions to prepare for my exams next year and this question (above) has stumped me. I genuinely don't know how to work this out. I know that a 64 bit machine is a lot faster than a 32 bit one but that's about it. Can anyone explain this? (Assume I am an idiot please)

  • 2
    $\begingroup$ "I know that a 64 bit machine is a lot faster than a 32 bit one but that's about it." -- that's wrong. One has little if anything to do with the other. This question is impossible to answer without knowing what CPU architecture you're referring to. $\endgroup$
    – Raphael
    Aug 7, 2015 at 11:03
  • $\begingroup$ If it has 64 data lines, it can load a double (= 64 bits) in one read cycle, so it should need 12. $\endgroup$
    – vonbrand
    Aug 7, 2015 at 12:47
  • $\begingroup$ Are you sure your question is copied accurately. I am no specialist, but on the net it seems that people talk of "data line" in the singular, and of $n$-bit data line. See this question answered by a hardware person. Telling us the level of your exam might also tell us what level of sophistication is needed to answer. What course is it, for what kind of curriculum. $\endgroup$
    – babou
    Aug 8, 2015 at 9:08

1 Answer 1


a double precision floating-point, is a 64-bit variable (as the question says: 8 bytes each = 64 bits).

If the CPU's bus width is 64bit, and assuming the memory has a data width of 64-bit, then exactly 12 read-cycles are needed to read 12 double-float variables, since at each cycle we can access 64-bits = 1 complete variable.

If, however, the memory has a data-width of 8 bits (every address gives back only 8 bits of data), then 1 double-float variable lays over 8 different addresses, and takes 8 cycles to read. Then, to read 12 different variables, the CPU needs to access 96 different addresses, i.e., 96 read-cycles.

If the parameters of the CPU/Memory are different, so does the answer.


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