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It is claimed in my textbook that

In a 32-bit system, The instruction LDR r4,[r6] lets you address a logical space of 4GB.

I know where the 4GB comes from, It is simply 2^32 / (1024 x 1024 x 1024).

However, My question is why is it bytes and not bits ?

Why when we raise 2^32, we should talk about bits and not bytes. And so 4GB doesn't make sense to me .

For me It would make sense if it is (2^32/8)/ (1024 x 1024 x 1024)

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That's because memory is usually byte-addressed. The address that you load from is an address of a byte in memory. Each address refers a different byte in memory. For a 32-bit address, there are $2^{32}$ different possibilities for the address, so $2^{32}$ different bytes that the address could refer to (and no overlap among these bytes). $2^{32}$ is equal to 4GB.

If we had a hypothetical machine where memory was bit-addressible, then it would indeed be 4Gb, i.e., 4 gigabits instead of 4 gigabytes -- but no one builds machines that way today.

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  • $\begingroup$ when you said 2^32 different possibilities for the address, so 2^32 different bytes. I still don't understand how it is 2^32 different bytes ? I Understand that they are 2^32 different addresses but I still don't get why they are different bytes ? :) $\endgroup$ – alkabary Aug 21 '15 at 21:30
  • $\begingroup$ @alkabary, I've updated my answer to try to explain that. If it's still unclear, can you elaborate more on why you don't see why they are different bytes? Can you describe an example scenario where they wouldn't be different bytes? That might help me make my answer clearer. It might be that I'm so used to this that I've forgotten why this isn't obvious. Thank you! $\endgroup$ – D.W. Aug 21 '15 at 21:32
  • $\begingroup$ [Nitpicking] Actually, some machines have bit adressable areas : electronics.stackexchange.com/questions/27550/…. $\endgroup$ – TEMLIB Aug 22 '15 at 1:00
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One needs to distinguish the address bus and the data bus.

The width of the address bus determines how many locations (=words) the system can access. For instance, with 32-bit address bus, the system can access $2^{32}$ different addresses, that is, 4G words.

The width of the data bus determines how many bits each word consists. If the data width is 32 bits then each word is 32bits (4 bytes). There are architectures where word size is a byte, bit, or even 64bits.

Unless otherwise mentioned, it makes sense that a "32bit system" has an address bus and data bus of 32 bits. But one needs to check the specifics to be sure.

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