In all the books, packets of slides and similar I read, cache miss is always explained by assuming that blocks of different caches (or cache and RAM) are always of the same size. It's pretty clear how it's works in this case but the question is: what if block dimensions are not equal among caches?
For example, assuming a L1 cache of 8KB and 16B blocks (that implies 2^9 blocks) and a L2 cache of 512KB with 32B block (that implies 2^14 blocks). Assuming that a load have to be executed, i.e. LD R1,(0x0000AFAF) and suppose that there is a cache L1 miss and a cache L2 hit, what happens? What I mean is that i know that a block containing that addressed byte would be stored in L1 cache and i know where. The problem is what i have to save. I mean, have i to save half block of L2 cache (from 0x0000AFA0 to 0x0000AFAF) in a block of L1 cache or have i to save a block of L2 cache (from 0x0000AFA0 to 0x0000AFBf) in two block of L1 cache? Would be the same if i had cache + RAM instead?